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= Stage 7 Trigger detection
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Due to the fact that triggering the signal in software was not sufficient enough, the triggering was implemented in hardware.
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In addition, the ETS feature is dependent on hardware triggering. ETS will be discussed in xy and xy.
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In addition, the ETS feature is dependent on hardware triggering. ETS will be discussed in https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory].
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{empty} +
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... | ... | @@ -14,7 +14,7 @@ This rising and falling edges of the output of the comparator can be analyzed by |
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The trigger level is set by the user at the Graphical User Interface (GUI). The GUI then sends a command to the FPGA or microcontroller to configure their PWM outputs.
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The duty cycle of the generated PWM signal then defines the voltage at the comparator and therefore the trigger level.
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To convert the PWM signal into a DC voltage, the signal is passed through a low pass filter.
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Figure 22 shows the section of the OpenLab front-end which contains the hardware trigger circuit.
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Figure 1 shows the section of the OpenLab front-end which contains the hardware trigger circuit.
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... | ... | @@ -32,12 +32,12 @@ The trigger level is simulated to be set to 0V by the GUI. Therefore, the PWM of |
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage7_ltspice.PNG[caption="Figure 1: ",title="Relation between IN and OUT of stage 7. The trigger level is 0V set by the GUI",align="center"]
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage7_ltspice.PNG[caption="Figure 2: ",title="Relation between IN and OUT of stage 7. The trigger level is 0V set by the GUI",align="center"]
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{empty} +
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The waveform shown in green illustrates the voltage of the trigger level after passing the lowpass filter. The voltage hits the target trigger level after the capacitor is fully charged.
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Due to the added offset (see stage 4, chapter 4.2.4), the trigger level is set to 1.75V. This is necessary to display the captured waveform in the PC application correctly. +
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Due to the added offset (see https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage4[Stage 4 Adding a Constant Offset to the Signal]), the trigger level is set to 1.75V. This is necessary to display the captured waveform in the PC application correctly. +
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0V trigger level configured by the GUI, translates to 1.75V (the virtual zero point) at the signal processing front-end.
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