|
|
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>]
|
|
|
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage6[<Stage 6 Impedance converter] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/RTS_theory[Real Time Sampling - Theory>]
|
|
|
|
|
|
= Stage 7 Trigger detection
|
|
|
|
... | ... | @@ -40,3 +40,7 @@ The waveform shown in green illustrates the voltage of the trigger level after p |
|
|
Due to the added offset (see stage 4, chapter 4.2.4), the trigger level is set to 1.75V. This is necessary to display the captured waveform in the PC application correctly. +
|
|
|
|
|
|
0V trigger level configured by the GUI, translates to 1.75V (the virtual zero point) at the signal processing front-end.
|
|
|
|
|
|
{empty} +
|
|
|
|
|
|
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage6[<Stage 6 Impedance converter] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/RTS_theory[Real Time Sampling - Theory>] |