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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>]
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage6[<Stage 6 Impedance converter] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/RTS_theory[Real Time Sampling - Theory>]
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= Stage 7 Trigger detection
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... | ... | @@ -39,4 +39,8 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci |
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The waveform shown in green illustrates the voltage of the trigger level after passing the lowpass filter. The voltage hits the target trigger level after the capacitor is fully charged.
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Due to the added offset (see stage 4, chapter 4.2.4), the trigger level is set to 1.75V. This is necessary to display the captured waveform in the PC application correctly. +
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0V trigger level configured by the GUI, translates to 1.75V (the virtual zero point) at the signal processing front-end. |
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\ No newline at end of file |
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0V trigger level configured by the GUI, translates to 1.75V (the virtual zero point) at the signal processing front-end.
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{empty} +
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage6[<Stage 6 Impedance converter] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/RTS_theory[Real Time Sampling - Theory>] |