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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>]
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= Stage 3 Variable Amplification
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To be able to measure signals within a wide input voltage range, a variable amplification stage is mandatory. This stage will, depending on the signal amplitude, amplify or attenuate the signal.
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This ensures that the ADC, at the end of the front-end, always samples at nearly full scale.
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Because of the characteristics of the chosen ADCs of the OpenLab front-end, the acceptable input range is defined as 0V to 3.3V.
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This includes the external ADCs, needed by the FPGA-based solution, as well as the integrated ADCs of the microcontroller-based solution.
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As a side effect of the ADC input protection stage, the input range of the ADC is limited from 0.8V to 2.7V.
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The reason for this limitation is the characteristics of standard silicon-based diodes. Diodes will not start to clip voltages at a strict defined level.
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The signal that is passed through the protection stage will get distorted in connection with the characteristic curve of the used diode.
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In case of the OpenLab front-end, signals with a voltage range outside of 0.8V – 2.7V will get distorted.
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So the voltage of the measured signal has to be prepared by the variable amplification stage to fulfill the previously mentioned limitations.
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This is done by changing the gain-level of stage 3, depending on the amplitude of the input signal.
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Figure 16, shows the schematic of stage 3. It includes the op-amp and the amplification stage selection circuit.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage3.PNG[caption="Figure 1: ",title="Schematic of stage 3 of the OpenLab oscilloscope front-end",align="center"]
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The gain level is selected by changing the ratio of the voltage divider of the non-inverting operational amplifier. A simplified version of this circuit is illustrated in figure 17.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage3_OPV.PNG[caption="Figure 2: ",title="Schematic of a non-inverting op-amp circuit (simplification of stage 3)",align="center"]
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By applying the formula of a standard non-inverting op-amp, the gain level (AV ) can be calculated as shown in the following calculation.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage3_formula.PNG[caption="Formula 1: ",title="Formula for calculating the gain level of a standard non-inverting op-amp",align="center"]
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In case of the OpenLab front-end the resistance of Rgadj is changed by switching through various resistors, while Rf stays at a fixed value. This will adjust the desired amplification accordingly.
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Rgadj is changed by opening or closing the ground connection through bipolar transistors.
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Those transistors on the other hand, are controlled by a de-multiplexer which is directly accessed by the development board.
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This applies to the FPGA-based oscilloscope as well as to the microcontroller-based solution. +
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The correct values of Rgadj , at each amplification stage, were calculated and summarized in table 5.
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This listing also mentions the gain of each amplification stage and at what input voltage range it is used for.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage3_table.PNG[caption="Figure 3: ",title="Various gain settings regarding stage 3 and its relation to different input signal amplitudes",align="center"]
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As can be seen in table 5, the output voltage range of each amplification stage varies from stage to stage. This could be minimized by using resistors of a higher class.
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The OpenLab oscilloscope uses resistors of the E12 or E24 series to reduce costs. This helps to achieve the low-cost status of the project. +
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Those variations of the output voltage are compensated in software to maintain correct measurements.
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The following chart, shown in figure 18, is an example of the input versus output waveform of stage 3.
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The test signal had the characteristics of a sinusoidal waveform with an amplitude of 5V and a frequency of 1kHz.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage3_ltspice.PNG[caption="Figure 4: ",title="Relation between IN and OUT of stage 3. The test signal is a 5V 1kHz sine",align="center"]
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The waveform drawn in red represents the input of stage 3. The output is shown by the blue signal. According to table 5, amplification stage 3 was selected.
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This will amplify the input signal of stage 3 by a factor of 3.68.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>] |