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This is done by changing the gain-level of stage 3, depending on the amplitude of the input signal.
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Figure 16, shows the schematic of stage 3. It includes the op-amp and the amplification stage selection circuit.
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Figure 1, shows the schematic of stage 3. It includes the op-amp and the amplification stage selection circuit.
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... | ... | @@ -23,7 +23,7 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci |
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The gain level is selected by changing the ratio of the voltage divider of the non-inverting operational amplifier. A simplified version of this circuit is illustrated in figure 17.
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The gain level is selected by changing the ratio of the voltage divider of the non-inverting operational amplifier. A simplified version of this circuit is illustrated in figure 2.
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... | ... | @@ -48,7 +48,7 @@ This listing also mentions the gain of each amplification stage and at what inpu |
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage3_table.PNG[caption="Figure 3: ",title="Various gain settings regarding stage 3 and its relation to different input signal amplitudes",align="center"]
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage3_table.PNG[caption="Table 1: ",title="Various gain settings regarding stage 3 and its relation to different input signal amplitudes",align="center"]
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... | ... | @@ -58,12 +58,12 @@ Those variations of the output voltage are compensated in software to maintain c |
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The following chart, shown in figure 18, is an example of the input versus output waveform of stage 3.
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The following chart, shown in figure 3, is an example of the input versus output waveform of stage 3.
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The test signal had the characteristics of a sinusoidal waveform with an amplitude of 5V and a frequency of 1kHz.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage3_ltspice.PNG[caption="Figure 4: ",title="Relation between IN and OUT of stage 3. The test signal is a 5V 1kHz sine",align="center"]
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage3_ltspice.PNG[caption="Figure 3: ",title="Relation between IN and OUT of stage 3. The test signal is a 5V 1kHz sine",align="center"]
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