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= Stage 2 Offset Compensation and Op-amp Input Stage
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This section of the circuit functions as a high impedance input for the first amplifier stage.
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As described in the previous chapter 4.1, the usage of a FET voltage follower is quite common in relation to oscilloscope front-ends.
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As described in the previous page xy, the usage of a FET voltage follower is quite common in relation to oscilloscope front-ends.
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Due to the fact that op-amps tend to add a small offset to their output signal, it is possible that the measured signal gets level shifted and therefore distorted.
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To encounter this and for calibration reasons, this stage got modified to compensate any unwanted offset.
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This was done by adding a potentiometer to the FET which is connected to the negative voltage source. The schematic of stage 2 is shown in figure 15.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage2.PNG[caption="Figure 1: ",title="Schematic of stage 2 of the OpenLab oscilloscope front-end",align="center"]
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If the value of the resistance of the potentiometer is higher than resistor R7, a positive offset will be added. The other way around a negative offset will be added.
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When the resistance of R7 is exactly the same as the combined resistance of R16 and RV1, the offset will be zero.
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With this potentiometer, minimal offset errors can be corrected in hardware.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>] |