OpenLab_osci_FPGA_imp2.asciidoc

@@ -46,6 +46,21 @@ It can be used in order to detect corrupted data packets, but uses bandwidth and
 Depending on the configuration of the UART interface, the stop bit can be 1, 1.5 or 2 bits long. The data rate depends on the selected baud rate.
 It declares the frequency at which one bit is transfered. Regarding the OpenLab oscilloscope, the UART communication is configured to use a 8 bit wide word, no parity bit and 1 stop bit.
 
+== Receive Component
+
+The receiving part of the UART implementation is directly connected to the RX line of the Transistor–Transistor Logic (TTL) serial adapter cable.
+This component detects incoming data by checking continually the status of the RX line. If it detects an falling edge, data is being sent to the FPGA.
+This is also known as the start bit of the serial communication, which is described in section 5.3.1.
+For correctly interpreting the sequence of bits, the FPGA has to store the information at the frequency of the baud rate.
+For example, to receive data at 1 MBaud, the system clock of the OpenLab FPGA design hast to be clocked down to 1 MHz. This is done by implementing a simple clock divider.
+At each clock cycle one bit of the received data package is stored into a register. After the stop bit was received, the "FINISHED" flag is set and the data is ready for further processing.
+
+== Transmit Component
+
+This component is structured in a similar way as the receiving part, explained in section 5.3.2. The 8 bit user data, that should be transfered, is applied as a parallel signal to this module.
+To prevent corrupted data, the transfer will only start after the "START" input signal is high.
+During transfer the "BUSY" line will be high to indicate that the transmitter is currently in use and the output data of the transmitter is not yet valid.
+
 
 
 == https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]