A widely used communication type is the standard UART serial communication. The DE0 evaluation board  features a RS232 level shifter, which converts the TTL voltages from the FPGA to RS232 levels. The MAX3232 level shifter limits the maximum transfer rate to 1 MBaud which is one reason for not using this component in the OpenLab project. Students at the UAS Technikum Wien generally use USB to TTL serial adapter cables, so RS232 voltage levels are not required.
For establishing a UART compatible serial communication, the FPGA design has to provide a parallel to serial data translation. In case of the OpenLab project, the SERIAL_COM_8N1 component serves as the UART interface. The component itself, as shown in figure 42, consists of two separate components which will be described in chapter 5.3.2 and 5.3.3.
This interface implementation is configured to transmit and receive data with a word size of 1 byte. The data that should be transfered to the host is given by the TX_DATA input of the SERIAL_COM_8N1 component. The transmit part then translates the information into UART compatible serial data and handles the transmission. The process of receiving data is done in a similar way. The received serial data is converted by the receive part of the SERIAL_COM_8N1 component and is provided as a 1 byte vector by RX_DATA. To start the transmission, TX_START has to be set in order to confirm that TX_DATA is stable and ready for transfer. The end of one transmission cycle is signaled by TX_FINISHED. A successfully received word is indicated by RX_FINISHED. The status of the transmit unit is shown by TX_BUSY in order to prevent data corruption.
The UART communication transmits bytes by splitting the data into their individual bits in order to transfer them sequentially over a single transmission line. Data is received by reversing the process. During idle, the transmission line is pulled high. The start of transmission is declared by sending the start bit as shown in figure 43. The receiver uses the start bit to detect the beginning of the next data package.
The next transmitted bits contain the data word and can vary in sizes between 5 to 9 bits. The parity bit is optional and not displayed in figure 43. It can be used in order to detect corrupted data packets, but uses bandwidth and therefore reduces the data rate. The end of one transmission cycle is declared by the stop bit. Depending on the configuration of the UART interface, the stop bit can be 1, 1.5 or 2 bits long. The data rate depends on the selected baud rate. It declares the frequency at which one bit is transfered. Regarding the OpenLab oscilloscope, the UART communication is configured to use a 8 bit wide word, no parity bit and 1 stop bit.
The receiving part of the UART implementation is directly connected to the RX line of the Transistor–Transistor Logic (TTL) serial adapter cable. This component detects incoming data by checking continually the status of the RX line. If it detects an falling edge, data is being sent to the FPGA. This is also known as the start bit of the serial communication, which is described in section 5.3.1. For correctly interpreting the sequence of bits, the FPGA has to store the information at the frequency of the baud rate. For example, to receive data at 1 MBaud, the system clock of the OpenLab FPGA design hast to be clocked down to 1 MHz. This is done by implementing a simple clock divider. At each clock cycle one bit of the received data package is stored into a register. After the stop bit was received, the "FINISHED" flag is set and the data is ready for further processing.
This component is structured in a similar way as the receiving part, explained in section 5.3.2. The 8 bit user data, that should be transfered, is applied as a parallel signal to this module. To prevent corrupted data, the transfer will only start after the "START" input signal is high. During transfer the "BUSY" line will be high to indicate that the transmitter is currently in use and the output data of the transmitter is not yet valid.