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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>]
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage5[<Stage 5 ADC Protection] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage7[Stage 7 Trigger detection>]
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= Stage 6 Impedance converter
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... | ... | @@ -11,4 +11,8 @@ Due to the added impedance of the previous stage, the impedance has to be conver |
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{empty} +
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This can be done by using an op-amp and connecting the output of the op-amp directly to the negative input terminal. This leads to a very low impedance input for the connected ADC. |
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\ No newline at end of file |
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This can be done by using an op-amp and connecting the output of the op-amp directly to the negative input terminal. This leads to a very low impedance input for the connected ADC.
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{empty} +
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage5[<Stage 5 ADC Protection] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage7[Stage 7 Trigger detection>] |