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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>]
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage4[<Stage 4 Adding a Constant Offset to the Signal] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage6[Stage 6 Impedance converter>]
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= Stage 5 ADC Protection
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... | ... | @@ -23,4 +23,8 @@ Due to the effects of the forward bias voltage drop, without an additional offse |
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This means that if a negative voltage is outputted by stage 4, the protection circuit will let negative voltages pass.
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To prevent this, an additional offset applied to the negative cutting diode is mandatory.
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This offset voltage is set a bit higher than the forward voltage of the diode (approx. 1V), so that the clipping engages early enough.
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Finally stage 5 will protect the ADCs from damage. |
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\ No newline at end of file |
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Finally stage 5 will protect the ADCs from damage.
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{empty} +
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage4[<Stage 4 Adding a Constant Offset to the Signal] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage6[Stage 6 Impedance converter>] |