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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>]
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage3[<Stage 3 Variable Amplification] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage5[Stage 5 ADC Protection>]
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= Stage 4 Adding a Constant Offset to the Signal
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... | ... | @@ -37,4 +37,8 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci |
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The input of stage 4, which is applied by stage 3, is represented by the red waveform. The output of stage 4 is shown in blue.
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As mentioned before, the third amplification stage was selected in order to correctly amplify the input signal.
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As shown in figure 2, the output of stage 4 is centered at 1.75V. This is the previously mentioned virtual zero point of the signal.
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It enables the measurement of negative signals with non-differential ADCs. |
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\ No newline at end of file |
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It enables the measurement of negative signals with non-differential ADCs.
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{empty} +
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage3[<Stage 3 Variable Amplification] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_stage5[Stage 5 ADC Protection>] |