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In case of the OpenLab front-end the resistance of Rgadj is changed by switching through various resistors, while Rf stays at a fixed value. This will adjust the desired amplification accordingly.
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Rgadj is changed by opening or closing the ground connection through bipolar transistors.
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Those transistors on the other hand, are controlled by a de-multiplexer which is directly accessed by the development board.
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This applies to the FPGA-based oscilloscope as well as to the microcontroller-based solution. +
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The correct values of Rgadj , at each amplification stage, were calculated and summarized in table 1.
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This listing also mentions the gain of each amplification stage and at what input voltage range it is used for.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage3_table.PNG[caption="Figure 3: ",title="Various gain settings regarding stage 3 and its relation to different input signal amplitudes",align="center"]
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As can be seen in table 1, the output voltage range of each amplification stage varies from stage to stage. This could be minimized by using resistors of a higher class.
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The OpenLab oscilloscope uses resistors of the E12 or E24 series to reduce costs. This helps to achieve the low-cost status of the project. +
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Those variations of the output voltage are compensated in software to maintain correct measurements.
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The following chart, shown in figure 18, is an example of the input versus output waveform of stage 3.
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The test signal had the characteristics of a sinusoidal waveform with an amplitude of 5V and a frequency of 1kHz.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/sig_proc_osci_hardware/sig_proc_osci_hardware_stage3_ltspice.PNG[caption="Figure 4: ",title="Relation between IN and OUT of stage 3. The test signal is a 5V 1kHz sine",align="center"]
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The waveform drawn in red represents the input of stage 3. The output is shown by the blue signal. According to table 1, amplification stage 3 was selected.
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This will amplify the input signal of stage 3 by a factor of 3.68.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_hardware[<Signal Processing Hardware] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory>] |