... | ... | @@ -21,7 +21,7 @@ After receiving the necessary parameters from the GUI, the FPGA has to collect a |
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== Analysing the input signal
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== Analysing the period of the input signal
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To determine the exact point in time at which the ADCs should be powered on, the period of the input signal has to be analyzed. This process is shown in figure 1.
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The input signal is represented by the first-, the output of the comparator by the second signal graph.
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... | ... | @@ -33,6 +33,19 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SET |
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The period of the input signal is determined by counting the system clock cycles of the FPGA between two detected trigger edges.
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If the counter reaches its maximum value, an out-of-trigger situation was detected.
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During ETS mode, the FPGA will automatically handle any signal that reaches a frequency below the minimum processable, as non-trigger able.
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This limitation varies between the selectable virtual sample rate settings.
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If no trigger was detected, the FPGA continuous further processing by assuming a very low frequency signal.
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So it is guaranteed that the GUI is able to display a waveform even during an out-of-trigger situation. At this time, the period of the input signal is unknown.
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Hence, the ADCs are not able to sample at the correct moment and the displayed waveform will be distorted. This behavior reflects the limitations of ETS and is not due to bad design.
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Without a suitable trigger information, a correct reconstruction of the input signal is impossible.
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If the FPGA would stop acquiring the input signal, the GUI won’t be able to refresh the displayed waveform. Thus the user may misinterpret this situation as a crash of the oscilloscope.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > |