... | ... | @@ -116,4 +116,25 @@ It describes the amount of time it takes the ADC to fully power-up and take one |
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The process of capturing the first sample in relation to the timing behaviour of the ADC is illustrated in figure 4.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_ETS_ADC_Timing.png[caption="Figure 4: ",title="Capturing samples during the first acquisition round (ETS)",height=400,align="center"]
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After the ADC captured the first sample, the acquisition continuous at maximum real-time sampling rate. This goes on until the current ETS packet is complete.
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This process is only valid while composing the first packet of one complete ETS cycle.
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For the remaining packets, the FPGA has to delay the point in time at which the ADC captures the first sample.
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This delay is specified by the virtual sample rate which is determined by the GUI.
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The delay indicates the time distance between two samples after complete reconstruction of the waveform.
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For details see https://es.technikum-wien.at/openlab/openlab_wiki/wikis/ETS_theory[Equivalent Time Sampling - Theory] and https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[Sequential Equivalent Time Samling - Theory].
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Depending on the settings, send by the GUI, the FPGA has to set the delay value for further processing. The FPGA delays the ADC acquisition by counting cycles of its system clock.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > |