... | ... | @@ -21,15 +21,52 @@ After receiving the necessary parameters from the GUI, the FPGA has to collect a |
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== Controlling the sampling of the ADS7885 ADC
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For acquiring in SETS mode the ADCs, which are controlled by the FPGA, have to sample at well-defined points in time.
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The selected ADCs are not able to perform in single-shot operation mode.
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That means that the ADCs are capturing samples continuously as long as the Chip-Select(CS) and Clock(CLK) inputs are correctly timed.
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A precise control, at which point in time the input signal is being captured, is not possible.
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In addition, the selected ADCs do not signal if the capture and conversion process during acquisition is complete.
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This information was added by the ADC interface entity of the FPGA design.
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The exact timing behaviour is known from the datasheet of the ADC and implemented into the interface component [1].
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In order to be able to control the timing of the ADC, it was necessary to define a known reference point.
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The only way to predict the point in time at which the ADC will take a sample, is by entering and leaving the power down mode.
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The duration of the warm-up phase after a power done cycle is precisely described by the datasheet [1].
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According to the datasheet, the power down mode is entered if CS goes high any time between the 2nd SCLK falling edge and the 10th SCLK falling edge.
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This process is shown in figure 1.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_ADC_power_down.JPG[caption="Figure 1: ",title="Timing details of the power-down process of the ADS7885 ADC (1)",height=350,align="center"]
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In order to leave the power down mode, the CS input of the ADC has to be low for more than 10 SCLK falling edges. According to the datasheet, the warm-up phase takes 800ns [28].
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During warm-up the output of the ADC will be invalid. This process is illustrated in figure 2.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_ADC_power_up.JPG[caption="Figure 2: ",title="Timing details of the power-up process of the ADS7885 ADC (1)",height=350,align="center"]
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After the device is fully powered again, the sampling will continue. This defined behaviour is used to precisely control the timing of the ADS7885 ADC.
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== Analysing the period of the input signal
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To determine the exact point in time at which the ADCs should be powered on, the period of the input signal has to be analyzed. This process is shown in figure 1.
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The input signal is represented by the first-, the output of the comparator by the second signal graph.
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The start and stop timings of the signal-period counter is shown by the time-line at the bottom of figure 1.
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The start and stop timings of the signal-period counter is shown by the time-line at the bottom of figure 3.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_signal_analysis.png[caption="Figure 1: ",title="Period analysis of the input signal (ETS)",height=350,align="center"]
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SETS_FPGA_signal_analysis.png[caption="Figure 3: ",title="Period analysis of the input signal (ETS)",height=350,align="center"]
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