... | ... | @@ -45,7 +45,7 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/SETS_FPGA/SET |
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In order to leave the power down mode, the CS input of the ADC has to be low for more than 10 SCLK falling edges. According to the datasheet, the warm-up phase takes 800ns [28].
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In order to leave the power down mode, the CS input of the ADC has to be low for more than 10 SCLK falling edges. According to the datasheet, the warm-up phase takes 800ns [1].
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During warm-up the output of the ADC will be invalid. This process is illustrated in figure 2.
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... | ... | @@ -60,7 +60,7 @@ After the device is fully powered again, the sampling will continue. This define |
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== Analysing the period of the input signal
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To determine the exact point in time at which the ADCs should be powered on, the period of the input signal has to be analyzed. This process is shown in figure 1.
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To determine the exact point in time at which the ADCs should be powered on, the period of the input signal has to be analyzed. This process is shown in figure 3.
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The input signal is represented by the first-, the output of the comparator by the second signal graph.
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The start and stop timings of the signal-period counter is shown by the time-line at the bottom of figure 3.
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... | ... | @@ -113,7 +113,7 @@ This information is represented in form of system clock cycles. |
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* ADC_POWERUP_TIME (*NADC_POWERUP*) is a fixed value taken from the datasheet of the ADS7885 ADC [28]. +
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* ADC_POWERUP_TIME (*NADC_POWERUP*) is a fixed value taken from the datasheet of the ADS7885 ADC [1]. +
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It describes the amount of time it takes the ADC to fully power-up and take one sample after a power-down phase. The value of this constant is represented in form of system clock cycles.
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... | ... | @@ -203,4 +203,10 @@ At this point the process will continue like previously described. |
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== Bibliography
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. TEXAS INSTRUMENTS: _ADS7885 Data Sheet_, 2008
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/SETS_theory[<Sequential Equivalent Time Samling - Theory] | Not set yet > |
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