The previous wiki page described the functionality and the different methods of ETS. This page covers the implementation of SETS acquisition method, on a FPGA based oscilloscope. Within the OpenLab project, a modified version of SETS was implemented.
The following sections explains how a waveform is captured and displayed using the SETS-mode of the OpenLab FPGA based oscilloscope.
To configure the FPGA design to acquire samples in SETS, the GUI has to send the necessary parameters using the OpenLab protocol. This is done as soon as the user leaves the time base in which the ADCs are able to sample at real time. Because of the selected ADCs, the maximum real time sample rate is 2.5 MSa/s. This sample rate is used, if the user selects 20 μs/div as time base. A time base smaller than this will require a higher sample rate which is only achievable using the SETS mode. After receiving the necessary parameters from the GUI, the FPGA has to collect additional information about the input signal.
For acquiring in SETS mode the ADCs, which are controlled by the FPGA, have to sample at well-defined points in time. The selected ADCs are not able to perform in single-shot operation mode. That means that the ADCs are capturing samples continuously as long as the Chip-Select(CS) and Clock(CLK) inputs are correctly timed. A precise control, at which point in time the input signal is being captured, is not possible. In addition, the selected ADCs do not signal if the capture and conversion process during acquisition is complete.
This information was added by the ADC interface entity of the FPGA design. The exact timing behaviour is known from the datasheet of the ADC and implemented into the interface component . In order to be able to control the timing of the ADC, it was necessary to define a known reference point. The only way to predict the point in time at which the ADC will take a sample, is by entering and leaving the power down mode. The duration of the warm-up phase after a power done cycle is precisely described by the datasheet . According to the datasheet, the power down mode is entered if CS goes high any time between the 2nd SCLK falling edge and the 10th SCLK falling edge. This process is shown in figure 1.
In order to leave the power down mode, the CS input of the ADC has to be low for more than 10 SCLK falling edges. According to the datasheet, the warm-up phase takes 800ns . During warm-up the output of the ADC will be invalid. This process is illustrated in figure 2.
After the device is fully powered again, the sampling will continue. This defined behaviour is used to precisely control the timing of the ADS7885 ADC.
To determine the exact point in time at which the ADCs should be powered on, the period of the input signal has to be analyzed. This process is shown in figure 3. The input signal is represented by the first-, the output of the comparator by the second signal graph. The start and stop timings of the signal-period counter is shown by the time-line at the bottom of figure 3.
The period of the input signal is determined by counting the system clock cycles of the FPGA between two detected trigger edges. If the counter reaches its maximum value, an out-of-trigger situation was detected. During ETS mode, the FPGA will automatically handle any signal that reaches a frequency below the minimum processable, as non-trigger able. This limitation varies between the selectable virtual sample rate settings.
If no trigger was detected, the FPGA continuous further processing by assuming a very low frequency signal. So it is guaranteed that the GUI is able to display a waveform even during an out-of-trigger situation. At this time, the period of the input signal is unknown. Hence, the ADCs are not able to sample at the correct moment and the displayed waveform will be distorted. This behavior reflects the limitations of ETS and is not due to bad design. Without a suitable trigger information, a correct reconstruction of the input signal is impossible. If the FPGA would stop acquiring the input signal, the GUI won’t be able to refresh the displayed waveform. Thus the user may misinterpret this situation as a crash of the oscilloscope.
After the period of the input signal is analyzed and saved in form of the counter value, the FPGA continues with calculating the timing information in order to control the ADCs. According to the Sequential Equivalent Time Samling - Theory, the first sample of the first ETS packet should be acquired at the same moment a trigger edge was detected. The ADS7885 ADC is not able to take one sample at a specific time. So the timing needs to be synchronized with the power-on and wake-up cycle of the ADC. The ADC needs 800ns to fully power up and take a sample after a power down phase. So the FPGA needs to power up the ADC 800ns before the next trigger edge will be registered.
Because of the fact that the input signal has to be repetitive, the FPGA can calculate the timing as follows:
ADC_CYCLE_START_CNT (NADC_START) determines the amount of system clock cycles the FPGA has to wait before the ADC can be powered on.
The FPGA will start to count the cycles after a valid trigger event was detected.
SIGNAL_LEARNING_CNT (NSIGNAL_LEARNING) represents the previously analysed period of the input signal.
This information is represented in form of system clock cycles.
ADC_POWERUP_TIME (NADC_POWERUP) is a fixed value taken from the datasheet of the ADS7885 ADC .
It describes the amount of time it takes the ADC to fully power-up and take one sample after a power-down phase. The value of this constant is represented in form of system clock cycles.
The process of capturing the first sample in relation to the timing behaviour of the ADC is illustrated in figure 4.
After the ADC captured the first sample, the acquisition continuous at maximum real-time sampling rate. This goes on until the current ETS packet is complete. This process is only valid while composing the first packet of one complete ETS cycle.
For the remaining packets, the FPGA has to delay the point in time at which the ADC captures the first sample.
This delay is specified by the virtual sample rate which is determined by the GUI.
The delay indicates the time distance between two samples after complete reconstruction of the waveform.
For details see Equivalent Time Sampling - Theory and Sequential Equivalent Time Samling - Theory.
Depending on the settings, send by the GUI, the FPGA has to set the delay value for further processing. The FPGA delays the ADC acquisition by counting cycles of its system clock.
Table 1 shows the possible settings and its relation to the delay set by the FPGA.
At 50MSa/s virtual sample rate, the FPGA is not able to set the correct delay between two samples. This is due to the restrictions of the system clock timing. 50MSa/s would require a time distance between two samples of exactly 20ns. This value cannot be reached by a system clock of 120Mhz. So the FPGA is sampling at 60MSa/s at this case. This does not affect measurement quality. The signal is correctly reconstructed by the GUI.
This delay, set by the GUI, is considered during the calculation of the ADC timing. The following calculations are valid for all ETS packets excluding the first packet.
The added delay is represented by Ndelay. Depending on the current packet number, a multiple of the delay is added to the calculation.
ETS_RESOLUTION is the time distance between two samples and is represented in system clock cycles. (see table 1)
Figure 5 illustrates the process of capturing sample data after the first ETS packet was acquired. It highlights the differences between acquiring during the first ETS packet and the packets after.
Tdel represents the delay that the FPGA adds after the first ETS packet was completed.
The third ETS packet will add 2Tdel as delay. The fourth 3Tdel and so on.
There is one situation which requires additional calculation in order to correctly control the timing of the ADC.
Signals with a smaller period time than the wake-up time of the ADC needs a slightly different approach.
For example if SIGNAL_LEARNING_CNT = 50 then the FPGA will calculate ADC_CYCLE_START_CNT = -30 which will be unprocessable.
By constantly adding the period time of the signal to the result of the first calculation, the result will be positive at some point. If the result is finally above zero, the value is considered as new SIGNAL_LEARNING_CNT value. At this point the process will continue like previously described.