This entity handles the sample data acquisition of the FPGA-based oscilloscope. It also handles
the triggering and performs the advanced ETS operations. The implementation of the ETS
feature is described in chapter 7. This section will only describe the real-time sampling mode
of this component.
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Figure 44 shows the in- and outputs of the sampling-data-and-triggering component.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_FPGA_imp/osci_FPGA_imp_TTL_UART.PNG[caption="Figure 1: ",title="Inputs and outputs overview of the sampling-data-and-triggering - component",align="center"]
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This entity is designed to be instantiated multiple times. Each instance than handles a channel
of the oscilloscope. In case of the OpenLab oscilloscope two channels are implemented.
The sampling-data-and-triggering entity directly controls one of the ADC interfaces. The component
is able to control the sample rate and manages the power modes of the ADCs. Each
sample is stored in one of the two FIFO – buffers. Both channels have their own FIFO – buffer
to enable parallel acquisition. One buffer can store 4096 words. One word is 9 bits in size. This
uncommon word size is used to store additional information beside the ADC data itself. This
will be explained in detail by the following paragraphs.
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Triggering is done by constantly listening to the rise or fall flag of the trigger edge detection
entity. According to the configured trigger channel and the trigger type, an internal flag will be
set if a trigger event was detected. In order to reduce false trigger events, the last sampled data
of the same channel, set as the trigger channel, is compared to the current sample data. In
case of a rising edge trigger event, the value of the current sample has to be higher than the
value of the last sample. If a valid trigger event was detected, the TRIGGER_FOUND flag is set.
This information is stored in the last bit of the 9-bit wide word of the FIFO – buffer. The first 8 bit
contains the data of the captured sample. The ninth bit declares whether the sample represents
the first sample after a trigger event or not. This enables the communication-protocol-interpreter
entity to detect the start point of a triggered signal.
