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try to fix OpenLab_osci_FPGA_imp2.asciidoc authored by Patrick Schmitt's avatar Patrick Schmitt
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OpenLab_osci_FPGA_imp2.asciidoc
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......@@ -55,12 +55,6 @@ For correctly interpreting the sequence of bits, the FPGA has to store the infor
For example, to receive data at 1 MBaud, the system clock of the OpenLab FPGA design hast to be clocked down to 1 MHz. This is done by implementing a simple clock divider.
At each clock cycle one bit of the received data package is stored into a register. After the stop bit was received, the "FINISHED" flag is set and the data is ready for further processing.
== Transmit Component
This component is structured in a similar way as the receiving part, explained in section 5.3.2. The 8 bit user data, that should be transfered, is applied as a parallel signal to this module.
To prevent corrupted data, the transfer will only start after the "START" input signal is high.
During transfer the "BUSY" line will be high to indicate that the transmitter is currently in use and the output data of the transmitter is not yet valid.
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]