| ... | ... | @@ -49,7 +49,9 @@ It declares the frequency at which one bit is transfered. Regarding the OpenLab |
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== Receive Component
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The receiving part of the UART implementation is directly connected to the RX line of the Transistor-Transistor Logic (TTL) serial adapter cable.
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This component detects incoming data by checking continually the status of the RX line.
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If it detects an falling edge, data is being sent to the FPGA. This is also known as the start bit of the serial communication, which is described in section 5.3.1.
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For correctly interpreting the sequence of bits, the FPGA has to store the information at the frequency of the baud rate.
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== Transmit Component
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