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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]
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= Data communication between FPGA and PC
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A widely used communication type is the standard UART serial communication. The DE0
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evaluation board [27] features a RS232 level shifter, which converts the TTL voltages from
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the FPGA to RS232 levels. The MAX3232 level shifter limits the maximum transfer rate to 1
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MBaud which is one reason for not using this component in the OpenLab project. Students at
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the UAS Technikum Wien generally use USB to TTL serial adapter cables, so RS232 voltage
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levels are not required.
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{empty} +
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For establishing a UART compatible serial communication, the FPGA design has to provide a
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parallel to serial data translation. In case of the OpenLab project, the SERIAL_COM_8N1 component
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serves as the UART interface. The component itself, as shown in figure 42, consists of
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two separate components which will be described in chapter 5.3.2 and 5.3.3.
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{empty} +
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_FPGA_imp/osci_FPGA_imp_TTL_UART.PNG[caption="Figure 1: ",title="FPGA design structure of the UART TTL communication",align="center"]
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{empty} +
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This interface implementation is configure to transmit and receive data with a word size of
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1 byte. The data that should be transfered to the host is given by the TX_DATA input of
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the SERIAL_COM_8N1 component. The transmit part then translates the information into
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UART compatible serial data and handles the transmission. The process of receiving data
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is done in a similar way. The received serial data is converted by the receive part of the SERIAL_
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COM_8N1 component and is provided as a 1 byte vector by RX_DATA. To start the transmission,
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TX_START has to be set in order to confirm that TX_DATA is stable and ready for transfer.
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The end of one transmission cycle is signaled by TX_FINISHED. A successfully received
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word is indicated by RX_FINISHED. The status of the transmit unit is shown by TX_BUSY in
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order to prevent data corruption.
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{empty} +
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== UART - data frame
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The UART communication transmits bytes by splitting the data into their individual bits in order
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to transfer them sequentially over a single transmission line. Data is received by reversing the
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process. During idle, the transmission line is pulled high. The start of transmission is declared
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by sending the start bit as shown in figure 43. The receiver uses the start bit to detect the
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beginning of the next data package.
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{empty} +
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_FPGA_imp/osci_FPGA_imp_UART_frame.PNG[caption="Figure 1: ",title="UART data frame",align="center"]
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{empty} +
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The next transmitted bits contain the data word and can vary in sizes between 5 to 9 bits.
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The parity bit is optional and not displayed in figure 43. It can be used in order to detect
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corrupted data packets, but uses bandwidth and therefore reduces the data rate. The end of
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one transmission cycle is declared by the stop bit. Depending on the configuration of the UART
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interface, the stop bit can be 1, 1.5 or 2 bits long. The data rate depends on the selected baud
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rate. It declares the frequency at which one bit is transfered.
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Regarding the OpenLab oscilloscope, the UART communication is configured to use a 8 bit
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wide word, no parity bit and 1 stop bit.
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== Receive - Component
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The receiving part of the UART implementation is directly connected to the RX line of the
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Transistor–Transistor Logic (TTL) serial adapter cable. This component detects incoming data
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by checking continually the status of the RX line. If it detects an falling edge, data is being sent
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to the FPGA. This is also known as the start bit of the serial communication, which is described
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in section 5.3.1. For correctly interpreting the sequence of bits, the FPGA has to store the
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information at the frequency of the baud rate.
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For example, to receive data at 1 MBaud, the system clock of the OpenLab FPGA design
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hast to be clocked down to 1 MHz. This is done by implementing a simple clock divider. At
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each clock cycle one bit of the received data package is stored into a register. After the stop bit
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was received, the "FINISHED" flag is set and the data is ready for further processing.
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== Transmit - Component
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This component is structured in a similar way as the receiving part, explained in section 5.3.2.
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The 8 bit user data, that should be transfered, is applied as a parallel signal to this module. To
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prevent corrupted data, the transfer will only start after the "START" input signal is high. During
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transfer the "BUSY" line will be high to indicate that the transmitter is currently in use and the
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output data of the transmitter is not yet valid.
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== Transfer Rate and Data Integrity
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The maximum achievable stable transfer rate of the SERIAL_COM_8N1 component, is 2
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MBaud. However, the FPGA is theoretical capable of much higher data rates.
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Further tests revealed that at some host PCs during a 2 MBaud data transmission, some
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packets sent from the FPGA were not received. This is due to the fact that the machine was not
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able to clear its receiving buffer fast enough. Current data in the buffer will then be overwritten
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by new packets. In order to prevent this, the baud rate of the UART communication component
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can be switched between preconfigured settings. The baud rate can be selected between 1.2
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MBaud, 1.5 MBaud and 2 MBaud. As the default setting, 1.5 MBaud was chosen to be the most
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reliable transfer speed in relation to different kinds of PCs and operating systems.
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>] |
