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  • OpenLab_osci_FPGA_imp2

OpenLab_osci_FPGA_imp2 · Changes

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added content to OpenLab_osci_FPGA_imp2.asciidoc authored Mar 09, 2017 by Patrick Schmitt's avatar Patrick Schmitt
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]
= Data communication between FPGA and PC
A widely used communication type is the standard UART serial communication. The DE0
evaluation board [27] features a RS232 level shifter, which converts the TTL voltages from
the FPGA to RS232 levels. The MAX3232 level shifter limits the maximum transfer rate to 1
MBaud which is one reason for not using this component in the OpenLab project. Students at
the UAS Technikum Wien generally use USB to TTL serial adapter cables, so RS232 voltage
levels are not required.
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For establishing a UART compatible serial communication, the FPGA design has to provide a
parallel to serial data translation. In case of the OpenLab project, the SERIAL_COM_8N1 component
serves as the UART interface. The component itself, as shown in figure 42, consists of
two separate components which will be described in chapter 5.3.2 and 5.3.3.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_FPGA_imp/osci_FPGA_imp_TTL_UART.PNG[caption="Figure 1: ",title="FPGA design structure of the UART TTL communication",align="center"]
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This interface implementation is configure to transmit and receive data with a word size of
1 byte. The data that should be transfered to the host is given by the TX_DATA input of
the SERIAL_COM_8N1 component. The transmit part then translates the information into
UART compatible serial data and handles the transmission. The process of receiving data
is done in a similar way. The received serial data is converted by the receive part of the SERIAL_
COM_8N1 component and is provided as a 1 byte vector by RX_DATA. To start the transmission,
TX_START has to be set in order to confirm that TX_DATA is stable and ready for transfer.
The end of one transmission cycle is signaled by TX_FINISHED. A successfully received
word is indicated by RX_FINISHED. The status of the transmit unit is shown by TX_BUSY in
order to prevent data corruption.
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== UART - data frame
The UART communication transmits bytes by splitting the data into their individual bits in order
to transfer them sequentially over a single transmission line. Data is received by reversing the
process. During idle, the transmission line is pulled high. The start of transmission is declared
by sending the start bit as shown in figure 43. The receiver uses the start bit to detect the
beginning of the next data package.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_FPGA_imp/osci_FPGA_imp_UART_frame.PNG[caption="Figure 1: ",title="UART data frame",align="center"]
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The next transmitted bits contain the data word and can vary in sizes between 5 to 9 bits.
The parity bit is optional and not displayed in figure 43. It can be used in order to detect
corrupted data packets, but uses bandwidth and therefore reduces the data rate. The end of
one transmission cycle is declared by the stop bit. Depending on the configuration of the UART
interface, the stop bit can be 1, 1.5 or 2 bits long. The data rate depends on the selected baud
rate. It declares the frequency at which one bit is transfered.
Regarding the OpenLab oscilloscope, the UART communication is configured to use a 8 bit
wide word, no parity bit and 1 stop bit.
== Receive - Component
The receiving part of the UART implementation is directly connected to the RX line of the
Transistor–Transistor Logic (TTL) serial adapter cable. This component detects incoming data
by checking continually the status of the RX line. If it detects an falling edge, data is being sent
to the FPGA. This is also known as the start bit of the serial communication, which is described
in section 5.3.1. For correctly interpreting the sequence of bits, the FPGA has to store the
information at the frequency of the baud rate.
For example, to receive data at 1 MBaud, the system clock of the OpenLab FPGA design
hast to be clocked down to 1 MHz. This is done by implementing a simple clock divider. At
each clock cycle one bit of the received data package is stored into a register. After the stop bit
was received, the "FINISHED" flag is set and the data is ready for further processing.
== Transmit - Component
This component is structured in a similar way as the receiving part, explained in section 5.3.2.
The 8 bit user data, that should be transfered, is applied as a parallel signal to this module. To
prevent corrupted data, the transfer will only start after the "START" input signal is high. During
transfer the "BUSY" line will be high to indicate that the transmitter is currently in use and the
output data of the transmitter is not yet valid.
== Transfer Rate and Data Integrity
The maximum achievable stable transfer rate of the SERIAL_COM_8N1 component, is 2
MBaud. However, the FPGA is theoretical capable of much higher data rates.
Further tests revealed that at some host PCs during a 2 MBaud data transmission, some
packets sent from the FPGA were not received. This is due to the fact that the machine was not
able to clear its receiving buffer fast enough. Current data in the buffer will then be overwritten
by new packets. In order to prevent this, the baud rate of the UART communication component
can be switched between preconfigured settings. The baud rate can be selected between 1.2
MBaud, 1.5 MBaud and 2 MBaud. As the default setting, 1.5 MBaud was chosen to be the most
reliable transfer speed in relation to different kinds of PCs and operating systems.
== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]
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  • ETS_theory
  • OpenLab_RCL_uC_imp
  • OpenLab_SignalToolkit
  • OpenLab_UI_source_uC_imp
  • OpenLab_firm_ip_intro
  • OpenLab_logic_uC_imp
  • OpenLab_osci_FPGA_imp
  • OpenLab_osci_FPGA_imp1
  • OpenLab_osci_FPGA_imp2
  • OpenLab_osci_FPGA_imp3
  • OpenLab_osci_FPGA_imp4
  • OpenLab_osci_LPC_imp
  • OpenLab_osci_TIVAC_imp
  • OpenLab_osci_XMC_imp
  • OpenLab_siggen_ATMEL_imp
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