OpenLab_osci_FPGA_imp1.asciidoc

@@ -68,6 +68,29 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_
 
 {empty} +
 
+The incoming data, which is received by the data communication entity, is first analyzed by the Commander Interpreter - process.
+If the collected data represents a valid command, the CRC of the command is being verified. If the calculated CRC value is equal to the received value, the packet is considered as valid.
+Next, the Command Execution State Machine gets informed that a new command was received. Depended on the received command code, the state machine controller will change the active state.
+The state machine will then prepare the reply message. If the data is ready, the state machine starts the transmission of the message by setting a start flag.
+This flag is checked by the Reply Transmitter - process. This process accesses the data created by the state machine and transmits the complete message.
+The following paragraphs will give a more precise description of how each process is implemented.
 
+{empty} +
+
+=== Command Interpreter
+
+This process fetches the data received by the data communication entity. It composes every received byte to form the command send by the GUI.
+The data received is stored in a std_logic_vector array receive buffer. Due to the fact that a standard 8N1 serial connection is used, every received word is exactly 8 bits or 1 byte in size.
+After a command was successfully received by the Command Interpreter, the process will inform the Command Execution State Machine to set internal parameters and generate a reply message.
+
+{empty} +
+
+Figure 40 illustrates the flow diagram of the Command Interpreter - process.
+
+{empty} +
+
+image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_FPGA_imp/osci_FPGA_imp_cmd_flow.PNG[caption="Figure 1: ",title="Flow diagram of the command interpreter process as part of the FPGA design",align="center"]
+
+{empty} +
 
 == https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]