OpenLab_osci_FPGA_imp1.asciidoc

@@ -138,6 +138,8 @@ generating reply messages and prevents corrupted data during the power up phase.
 values of the two dummy bytes are considered as don't care. This state is only reached
 once during power up and cannot be reached during normal operation.
 
+{empty} +
+
 * IDLE
 
 This state is reached after successfully transferring the dummy message. It is used to
@@ -152,6 +154,8 @@ active and therefore data transmission is undesired. The IDLE state is also reac
 of the following states successfully complete execution: REPLY_HWV, REPLY_SWV and
 ACK.
 
+{empty} +
+
 * CHECK_DATA
 
 After a new command was received, this state will change the next state depended on the
@@ -163,6 +167,8 @@ If the command code is not equal to any valid code, this state will set the erro
 UNKNOWN_COMMAND and changes the next state to NACK. CHECK_DATA is reached
 every time a new command was received.
 
+{empty} +
+
 * WAIT_PC_REC
 
 Every time a sample data packet was send by the FPGA, the actual state switches to
@@ -172,6 +178,8 @@ After completing execution of the WAIT_PC_REC state, the current state switches
 to the REPLY_SD state. This will continue the transmission of sample data. This wait
 procedure can be interrupted by any incoming command.
 
+{empty} +
+
 * WAIT_NACK_FIN
 
 This state is reached after a NACK message was sent by the FPGA. It resets some
@@ -179,6 +187,8 @@ internal signals and variables to prepare the state machine for any new command.
 state machine will stay in this state as long as no new valid command was received by the
 Command Interpreter.
 
+{empty} +
+
 * CMD_STS
 
 This state gets activated by the CHECK_DATA state only. It will be reached after receiving
@@ -187,6 +197,8 @@ of the received command and applies any changes to the trigger system. Settings
 current active trigger channel, the trigger type and the trigger level are extracted from the
 payload data. After completion the next state changes to the ACK state.
 
+{empty} +
+
 * CMD_SCS
 
 After the command SET CHANNEL SETTINGS is received by the Command Interpreter,
@@ -200,6 +212,8 @@ from the SET CHANNEL SETTINGS message. The amplification-stage selection process
 is described in chapter 4.2.3 of this thesis. After execution, the CMD_SCS state will set
 the next state to ACK.
 
+{empty} +
+
 * CMD_STB
 
 The state machine will switch to the CMD_STB state if the SET TIME BASE command
@@ -212,6 +226,8 @@ to wait before storing a new sample. So complex mathematical operations are not
 The sampling procedure will be discussed in chapter 5.4. After completion, the next
 state changes to the ACK state.
 
+{empty} +
+
 * CMD_SSM
 
 This state gets activated by the CHECK_DATA state if the SET SAMPLING MODE command
@@ -221,6 +237,8 @@ description of ETS can be found in chapter 6. The implementation of the ETS samp
 mode is described in chapter 7. Again, after completion, the next state will be changed to
 the ACK state.
 
+{empty} +
+
 * REPLY_SD
 
 This state is responsible for reading the sample data provided by the sampling-data-andtriggering