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  • OpenLab_osci_FPGA_imp1

OpenLab_osci_FPGA_imp1 · Changes

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added content to OpenLab_osci_FPGA_imp1.asciidoc and removed OpenLab_osci_FPGA_imp5.asciidoc authored Mar 09, 2017 by Patrick Schmitt's avatar Patrick Schmitt
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......@@ -93,4 +93,36 @@ image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_
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The process starts first with the header of the command. If any data during the assemble phase is detected as invalid, the Command Interpreter will stop collecting data and restarts.
If the structure of the header is valid, the interpreter starts the CRC calculation process by setting a flag.
If the result of the CRC calculation is equal to the CRC value of the received header, the interpreter continuous. The interpreter will stop immediately if a CRC error is detected.
In that case, the interpreter will inform the Command Execution State Machine to prepare a NOT-ACKNOWLEDGE message.
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Depended on the value of the payload size field of the received command, the interpreter will fetch the payload data.
Due to the variable nature of the payload field, a value range check cannot be performed. The received data is again stored in a std_logic_vector array.
If the complete payload of the sent command is received, the CRC will be calculated.
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The procedure is exactly the same as for calculating the header CRC of the received command. Only if the results prove a valid packet, the processing continuous.
If both, the header and the payload of the command, is considered as valid, the interpreter will flag the received packet as valid and complete.
In order to inform the Command Execution State Machine, the Command Interpreter will set the PACKET_AVAILABLE flag.
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=== Command Execution State Machine
This process is responsible for executing the command received from the GUI. The process continuously listens to the Command Interpreter to instantly execute a new available command.
If a new packet was received, the state machine will first check the command code.
According to the value of the command code, the next state will execute the command and generate the corresponding reply.
The structure of the state machine is described by the following diagram seen in figure 41.
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image::https://es.technikum-wien.at/openlab/openlab_wiki/wikis/img/OpenLab_osci_FPGA_imp/osci_FPGA_imp_proto_SM.PNG[caption="Figure 1: ",title="Diagram of the command execution state machine",align="center"]
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== https://es.technikum-wien.at/openlab/openlab_wiki/wikis/home[Home] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/board_TIVAC[<Microcontroller-based TIVAC] | https://es.technikum-wien.at/openlab/openlab_wiki/wikis/sig_proc_osci_hardware[Signal Processing Front-End (XMC,TIVAC,DE0-Oscilloscope)>]
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  • ETS_theory
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  • OpenLab_SignalToolkit
  • OpenLab_UI_source_uC_imp
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  • OpenLab_osci_FPGA_imp3
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