@@ -23,9 +23,9 @@ If the received command includes directions for other components of the FPGA, th
{empty} +
For example, if the command "Set Channel Settings" is sent and the ON/OFF flag is set, the sampling entity of the FPGA has to transfer sample data into the FIFO – buffer.
For example, if the command "Set Channel Settings" is sent and the ON/OFF flag is set, the sampling entity of the FPGA has to transfer sample data into the FIFO - buffer.
The protocol interpreter itself then generates a reply message including the sampled data.
For each oscilloscope channel there is one instance of the sampling entity, the FIFO – buffer, trigger edge detection and the ADC interface.
For each oscilloscope channel there is one instance of the sampling entity, the FIFO - buffer, trigger edge detection and the ADC interface.
This enables the design to simultaneously capture sample data of multiple channels. The PWM generator gets two times instantiated.
The first instance handles the trigger level control. The second instance is responsible for the probe compensation.
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@@ -36,7 +36,7 @@ The following weblinks will link you to the websites describing the main compone
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp1[Protocol Interpreter and Reply Generator]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp2[Data communication between FPGA and PC]
* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp3[Sampling data and triggering]
