... | ... | @@ -23,9 +23,9 @@ If the received command includes directions for other components of the FPGA, th |
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For example, if the command "Set Channel Settings" is sent and the ON/OFF flag is set, the sampling entity of the FPGA has to transfer sample data into the FIFO – buffer.
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For example, if the command "Set Channel Settings" is sent and the ON/OFF flag is set, the sampling entity of the FPGA has to transfer sample data into the FIFO - buffer.
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The protocol interpreter itself then generates a reply message including the sampled data.
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For each oscilloscope channel there is one instance of the sampling entity, the FIFO – buffer, trigger edge detection and the ADC interface.
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For each oscilloscope channel there is one instance of the sampling entity, the FIFO - buffer, trigger edge detection and the ADC interface.
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This enables the design to simultaneously capture sample data of multiple channels. The PWM generator gets two times instantiated.
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The first instance handles the trigger level control. The second instance is responsible for the probe compensation.
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... | ... | @@ -36,7 +36,7 @@ The following weblinks will link you to the websites describing the main compone |
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* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp1[Protocol Interpreter and Reply Generator]
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* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp2[Data communication between FPGA and PC]
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* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp3[Sampling data and triggering]
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* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp4[ADC - interface]
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* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp4[ADC interface]
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* https://es.technikum-wien.at/openlab/openlab_wiki/wikis/OpenLab_osci_FPGA_imp5[Trigger edge detect]
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