- do not create vectored intermediate net if that's not needed.
 - instrument driving ports (almost) correctly

Still has quite some issues, namely:

 - instrumenting individual assignments of vectors does not work correctly
   because the rest of the net will not be assigned to the intermediate net.
 - instrumenting ports of the respective module changes the name of the port
   which obviously breaks the instantiation without further work.

by conserving the bit of instrumented busses in _get_net_connections_from_path()

Also, make sure we detect them as connected at all in case of spaces around the ~.
That should not happen with Verilog::Perl anyway...

Another lot remains... ;)

Also, retrieve unsorted parser elements in FIJI netlist.
The Verilog::Perl functions with the _sorted do sort their return values.
However, the order usually does not matter to us at all.

Port validation
Checking if port name not already in use
fiji_instrument.pl:
Toplevel module retrieved by FIJI::Netlist

Reapplied Beautify script

Logging to textbox in fiji download GUI
Added demo test configuration file

Added logging to Tk::Text widget

Added Button to validate/select Net Drivers for FIUs
Added MenuBar, TODO: decide if we use this

Added GUI features for fiji_setup: Choose port names, choose drivers upon save, validate drivers.
Added driver type and path to INI files.