- do not create vectored intermediate net if that's not needed.
 - instrument driving ports (almost) correctly

Still has quite some issues, namely:

 - instrumenting individual assignments of vectors does not work correctly
   because the rest of the net will not be assigned to the intermediate net.
 - instrumenting ports of the respective module changes the name of the port
   which obviously breaks the instantiation without further work.

Else synplify hollers (and rightly so)

Config::Simple intentionally removes trailing spaces m(
Solution: add quotes if need be... appatently they get removed automatically as well!

by conserving the bit of instrumented busses in _get_net_connections_from_path()

Also, make sure we detect them as connected at all in case of spaces around the ~.
That should not happen with Verilog::Perl anyway...

FIJI Net Selection displays busy cursor while matching nets, use HIERSEP in Settings Viewer and Netlist.pm consistently

This was done before... and proofed useful when I removed it *ahem*

else put them into the configuration file's directory as before

Another lot remains... ;)

Empty last parameter lead to warnings if other strings are empty.

and also possible is for non-fiu nets using the new dialog

Disable and remove old log file appender and respective log file when custom
log file is retrieved from FIJI settings.
Re-print command line arguments into custom log file when it gets activated.

Do not rely on synplify alone to diagnose problems but filter out warnings that
do not interest us. Implemented by grepping through the log file because
EDA tools suck.