- really abort on errors
- add .gitignore for generated files
- print path to relevant log files on errors
- do not print standard output of tools to focus on important stuff
- remove a leftover config file

Port validation
Checking if port name not already in use
fiji_instrument.pl:
Toplevel module retrieved by FIJI::Netlist

Reapplied Beautify script

Added logging to Tk::Text widget

Added functionality to export constraints files from fiji_instrument

Added port to Makefile so we don't have to edit test config files

Added demo file for download

todo: check if generated VHDL compiles and contains all necessary constants and assignments
todo: documentation
todo: beautify default assignments ($FIJI_DEFAULTS)