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vecs
FIJI Public
Commits
ffd9111d
Commit
ffd9111d
authored
Jul 02, 2015
by
Christian Fibich
Committed by
Stefan Tauner
May 04, 2018
Browse files
Cleaned up ->link() calls.
TODO: Check if this broke something (looks OK though)
parent
6f229307
Changes
1
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Inline
Side-by-side
FIJI/Netlist.pm
View file @
ffd9111d
...
...
@@ -63,6 +63,17 @@ my $FIJI_LOGO =<<logo_end;
// FIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJIFIJI
logo_end
#FIXME Verilog-Perl "link"ing...
# Linking a module
# ->links Ports, Cells, and Pins
#
# Linking a Port
# if port has no net assigned, assign net with matching name or create a new
# net. does not assign netname (needed for correct ->verilog_text output)
sub
new
($)
{
my
(
$class
)
=
@_
;
...
...
@@ -241,7 +252,8 @@ sub _add_port_to_hierarchy($$$;$) {
$np
->
userdata
(
FIJI::
VHDL
->
FIJI_USERDATA_FD_INDEX
,
$index
);
}
$nl
->
link
;
# let Verilog-Perl create a new net for the new port.
$startmod
->
link
;
# find all modules instantiating the current module
foreach
my
$mod
(
$nl
->
modules_sorted
)
{
...
...
@@ -250,8 +262,11 @@ sub _add_port_to_hierarchy($$$;$) {
$logger
->
debug
(
$indent
.
"
Adding pin
$name
to cell
"
.
$cell
->
name
);
$logger
->
debug
(
$indent
.
"
Connecting pin
"
.
$cell
->
name
.
$HIERSEP
.
$name
.
"
to port
"
.
$np
->
module
->
name
.
$HIERSEP
.
$np
->
name
);
$cell
->
new_pin
(
name
=>
$name
,
port
=>
$np
,
netname
=>
$np
->
net
->
name
);
$nl
->
link
;
portname
=>
$np
->
name
,
netname
=>
$np
->
net
->
name
);
# let verilog-perl find the net and port.
# FIXME sufficient to link "mod" here?
$mod
->
link
;
_add_port_to_hierarchy
(
$mod
,
$name
,
$function
,
$index
,
$indent
);
}
}
...
...
@@ -282,7 +297,7 @@ sub net_add_function ($$$;$) {
$logger
->
debug
("
Connecting Port
"
.
$op
->
name
.
"
to net
"
.
$net
->
name
);
$op
->
net
(
$net
);
#
$op->net($net);
should have a net already
$net
->
module
->
new_contassign
(
keyword
=>
"
assign
",
lhs
=>
$op
->
name
,
...
...
@@ -290,8 +305,6 @@ sub net_add_function ($$$;$) {
module
=>
$op
->
module
,
netlist
=>
$op
->
module
->
netlist
);
$self
->
{'
nl
'}
->
link
;
return
undef
;
}
...
...
@@ -365,7 +378,9 @@ sub instrument_net ($$;$) {
if
(
ref
(
$connection
)
eq
"
Verilog::Netlist::Pin
")
{
$log
.=
"
(output) pin
"
.
$connection
->
cell
->
name
.
$HIERSEP
.
$connection
->
name
;
$connection
->
netname
(
$op
->
net
->
name
);
$connection
->
net
(
$op
->
net
);
$connection
->
portname
(
$op
->
name
);
$connection
->
net
(
undef
);
# resolved by link
$connection
->
port
(
undef
);
# resolved by link
}
elsif
(
ref
(
$connection
)
eq
"
Verilog::Netlist::Port
")
{
$log
.=
"
(input) port
"
.
$connection
->
name
;
$connection
->
net
(
$op
->
net
);
...
...
@@ -380,7 +395,9 @@ sub instrument_net ($$;$) {
}
$log
.=
"
to generated output
"
.
$op
->
name
;
$logger
->
debug
(
$log
);
$self
->
{'
nl
'}
->
link
;
# create interconnections for newly created port/pin
# FIXME needed here or OK linking once after loop?
# $net->module->link;
}
# connecting newly created input to driven cells
...
...
@@ -389,7 +406,9 @@ sub instrument_net ($$;$) {
if
(
ref
(
$connection
)
eq
"
Verilog::Netlist::Pin
")
{
$log
.=
"
(input) pin
"
.
$connection
->
cell
->
name
.
$HIERSEP
.
$connection
->
name
;
$connection
->
netname
(
$ip
->
net
->
name
);
$connection
->
net
(
$ip
->
net
);
$connection
->
portname
(
$ip
->
name
);
$connection
->
net
(
undef
);
# resolved by link
$connection
->
port
(
undef
);
# resolved by link
}
elsif
(
ref
(
$connection
)
eq
"
Verilog::Netlist::Port
")
{
$log
.=
"
(output) port
"
.
$connection
->
module
->
name
.
$HIERSEP
.
$connection
->
name
;
$net
->
module
->
new_contassign
(
keyword
=>
"
assign
",
...
...
@@ -403,8 +422,13 @@ sub instrument_net ($$;$) {
}
$log
.=
"
to generated input
"
.
$ip
->
name
;
$logger
->
debug
(
$log
);
$self
->
{'
nl
'}
->
link
;
# create interconnections for newly created port/pin
# FIXME needed here or OK linking once after loop?
# $net->module->link;
}
# create interconnections for newly created ports/pins
# FIXME OK linking once after loop?
$net
->
module
->
link
;
return
undef
;
}
...
...
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