Commit fa8c624a authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Use net descriptor (net, netname, msb, lsb, module) instead of net only in generating

access to clock, reset, trigger and fault detect nets during instrumentation
parent 5076a062
......@@ -367,7 +367,7 @@ sub _add_port_to_hierarchy {
# 2. add a port through the entire hierarchy
# 3. assign the net to the port using a contassign statement
#
# @param net the Verilog::Net object to be used
# @param net_descriptor a hash containing the keys 'net' => Net Object, 'net_name' => Net name string, 'msb', 'lsb', 'mod' => The module containing the net
# @param function the function out of FIJI::VHDL->FIJI_PORTTYPE_xxx
# @param port_name how the port shall be named (will be prefixed with "fiji_")
# @param index for some FIJI_PORTTYPEs, an index is needed (FIU and Fault Detect)
......@@ -375,13 +375,42 @@ sub _add_port_to_hierarchy {
# @returns undef
sub net_add_function {
my $logger = get_logger("");
my ($self, $net, $function, $port_name, $index) = @_;
my ($self, $net_descriptor, $function, $port_name, $index) = @_;
$logger->debug("Adding function to \"" . $net->module->name . "\", net \"" . $net->name . "\"");
if (ref($net_descriptor) ne "HASH") {
return $net_descriptor;
}
my $net = $net_descriptor->{'net'};
my $net_name = $net_descriptor->{'net_name'};
my $msb = $net_descriptor->{'msb'};
my $lsb = $net_descriptor->{'lsb'};
my $mod = $net_descriptor->{'mod'};
my $idx = '';
my $idx_postfix = '';
# We need to produce names for the i/o ports that route the signals
# to the FIC. To allow to instrument multiple indices of a single
# signal we need to make these names unique thus we even include the
# indices if used.
if (defined $msb && defined $lsb) {
if ($msb ne $lsb) {
# We dont support the instrumentation of vectors (only sinlge indices of busses).
return "The given net to instrument is a vector with multiple bits.\nThis is not supported.\nMaybe you want to instrument a single bit of said vector instead?";
# $idx = "[".$msb.":".$lsb."]";
# $idx_postfix = "_".$msb."_".$lsb."_";
} else {
$idx = "[".$msb."]";
$idx_postfix = "_".$msb."_";
}
}
$logger->debug("Adding function to \"" . $mod . "\", net \"" . $net_name . "\"");
my $prefix = "fiji_";
my $unique_name = _unique_name($net->module,$prefix.$port_name);
my $unique_name = _unique_name($mod,$prefix.$port_name);
if (!defined $unique_name) {
$logger->error("Could not find a unique name for prefix ".$prefix.$port_name)
......@@ -390,13 +419,13 @@ sub net_add_function {
$logger->debug("\"" . $unique_name . "\" can be used as fiji connector");
my $op = _add_port_to_hierarchy($net->module, $unique_name, $function, $index);
$logger->debug("Connecting Port \"" . $op->name . "\" to net \"" . $net->name . "\"");
$logger->debug("Connecting Port \"" . $op->name . "\" to net \"" . $net_name.$idx . "\"");
# connect the net to the newly created port
$net->module->new_contassign(
keyword => "assign",
lhs => $op->name,
rhs => $net->name,
rhs => $net_name.$idx,
module => $op->module,
netlist => $op->module->netlist
);
......
......@@ -204,13 +204,13 @@ sub main {
# Clock net
$logger->info("Adding CLOCK net");
my $clk_net = $nl->get_net_from_path($settings_ref->{'design'}->{'CLOCK_NET'});
if (!blessed($clk_net) || !$clk_net->isa("Verilog::Netlist::Net")) {
$logger->error($clk_net);
my $clk_net_descriptor = $nl->get_netdescriptor_from_path($settings_ref->{'design'}->{'CLOCK_NET'});
if (ref($clk_net_descriptor) ne 'HASH') {
$logger->error($clk_net_descriptor);
return 1;
}
my $ret = $nl->net_add_function($clk_net, FIJI::VHDL->FIJI_PORTTYPE_CLOCK, "clock_from_dut_o");
my $ret = $nl->net_add_function($clk_net_descriptor, FIJI::VHDL->FIJI_PORTTYPE_CLOCK, "clock_from_dut_o");
if ($ret) {
$logger->error($ret);
return 1;
......@@ -220,13 +220,13 @@ sub main {
if ($settings_ref->{'design'}->{'RESET_DUT_OUT_EN'} == 1) {
$logger->info("Adding RESET_DUT_OUT net");
my $rst_in_net = $nl->get_net_from_path($settings_ref->{'design'}->{'RESET_DUT_OUT_NAME'});
if (!blessed($rst_in_net) || !$rst_in_net->isa("Verilog::Netlist::Net")) {
$logger->error($rst_in_net);
my $rst_in_net_descriptor = $nl->get_netdescriptor_from_path($settings_ref->{'design'}->{'RESET_DUT_OUT_NAME'});
if (ref($rst_in_net_descriptor) ne 'HASH') {
$logger->error($rst_in_net_descriptor);
return 1;
}
my $ret = $nl->net_add_function($rst_in_net, FIJI::VHDL->FIJI_PORTTYPE_RESET_FROM_DUT, "reset_from_dut_o");
my $ret = $nl->net_add_function($rst_in_net_descriptor, FIJI::VHDL->FIJI_PORTTYPE_RESET_FROM_DUT, "reset_from_dut_o");
if ($ret) {
$logger->error($ret);
return 1;
......@@ -253,13 +253,13 @@ sub main {
if ($settings_ref->{'design'}->{'TRIGGER_DUT_EN'} == 1) {
$logger->info("Adding TRIGGER_DUT net");
my $rst_out_net = $nl->get_net_from_path($settings_ref->{'design'}->{'TRIGGER_DUT_NAME'});
if (!blessed($rst_out_net) || !$rst_out_net->isa("Verilog::Netlist::Net")) {
$logger->error($rst_out_net);
my $rst_out_net_descriptor = $nl->get_netdescriptor_from_path($settings_ref->{'design'}->{'TRIGGER_DUT_NAME'});
if (ref($rst_out_net_descriptor) ne 'HASH') {
$logger->error($rst_out_net_descriptor);
return 1;
}
my $ret = $nl->net_add_function($rst_out_net, FIJI::VHDL->FIJI_PORTTYPE_TRIGGER_FROM_DUT, "trigger_from_dut_o");
my $ret = $nl->net_add_function($rst_out_net_descriptor, FIJI::VHDL->FIJI_PORTTYPE_TRIGGER_FROM_DUT, "trigger_from_dut_o");
if ($ret) {
$logger->error($ret);
return 1;
......@@ -270,13 +270,13 @@ sub main {
if ($settings_ref->{'design'}->{'FAULT_DETECT_1_EN'} == 1) {
$logger->info("Adding FAULT_DETECT_1 net");
my $fd1_net = $nl->get_net_from_path($settings_ref->{'design'}->{'FAULT_DETECT_1_NAME'});
if (!blessed($fd1_net) || !$fd1_net->isa("Verilog::Netlist::Net")) {
$logger->error($fd1_net);
my $fd1_net_descriptor = $nl->get_netdescriptor_from_path($settings_ref->{'design'}->{'FAULT_DETECT_1_NAME'});
if (ref($fd1_net_descriptor) ne 'HASH') {
$logger->error($fd1_net_descriptor);
return 1;
}
my $ret = $nl->net_add_function($fd1_net, FIJI::VHDL->FIJI_PORTTYPE_FAULT_DETECTION, "fault_detect_1_o", 0);
my $ret = $nl->net_add_function($fd1_net_descriptor, FIJI::VHDL->FIJI_PORTTYPE_FAULT_DETECTION, "fault_detect_1_o", 0);
if ($ret) {
$logger->error($ret);
return 1;
......@@ -287,13 +287,13 @@ sub main {
if ($settings_ref->{'design'}->{'FAULT_DETECT_2_EN'} == 1) {
$logger->info("Adding FAULT_DETECT_2 net");
my $fd2_net = $nl->get_net_from_path($settings_ref->{'design'}->{'FAULT_DETECT_2_NAME'});
if (!blessed($fd2_net) || !$fd2_net->isa("Verilog::Netlist::Net")) {
$logger->error($fd2_net);
my $fd2_net_descriptor = $nl->get_netdescriptor_from_path($settings_ref->{'design'}->{'FAULT_DETECT_2_NAME'});
if (ref($fd2_net_descriptor) ne 'HASH') {
$logger->error($fd2_net_descriptor);
return 1;
}
my $ret = $nl->net_add_function($fd2_net, FIJI::VHDL->FIJI_PORTTYPE_FAULT_DETECTION, "fault_detect_2_o", 1);
my $ret = $nl->net_add_function($fd2_net_descriptor, FIJI::VHDL->FIJI_PORTTYPE_FAULT_DETECTION, "fault_detect_2_o", 1);
if ($ret) {
$logger->error($ret);
return 1;
......
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