Commit f8c3c981 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Added a script to generate a public config VHDL package from a fiji cfg file,

Modified Netlist.pm so that it prints possible drivers for all selected nets
while importing a netlist.
parent 4028b9a1
......@@ -63,11 +63,12 @@ sub get_nets ($) {
return $nets_ref;
}
sub _get_subnets ($$) {
my ($self, $nets_ref, $mod) = @_;
foreach my $n ($mod->nets) {
push(@{$nets_ref}, $n->name);
# FIXME what to do with bussed nets
$self->_get_possible_drivers($n,$mod);
}
foreach my $cell ($mod->cells_sorted) {
......@@ -77,4 +78,28 @@ sub _get_subnets ($$) {
}
}
sub _get_possible_drivers ($$) {
my ($self,$net,$mod) = @_;
print "Net ".$mod->name.".".$net->name.", possible drivers:\n";
foreach my $statement ($mod->statements) {
if($statement->lhs eq $net->name) {
# continuous assign statement to this net, there can't be another driver
print " assign: ".$mod->name.": ".$net->name." = ".$statement->rhs."\n";
return;
}
}
foreach my $port ($mod->ports_sorted) {
if (defined $port->net && $port->net == $net && $port->direction ne "out") {
print " port: ".$mod->name.".".$port->name."\n" ;
# driven from an input, there can't be another driver
return if ($port->direction eq "in")
}
}
foreach my $cell ($mod->cells_sorted) {
foreach my $pin ($cell->pins_sorted) {
print " pin: ".$mod->name.".".$pin->cell->name.".".$pin->name."\n" if (defined $pin->net && $pin->net == $net);
}
}
}
1;
; Config::Simple 4.58
; Mon May 4 16:02:25 2015
[FIU31]
NET_NAME=a
LFSR_MASK=0x0
FAULT_MODEL=RUNTIME
[FIU21]
NET_NAME=a
LFSR_MASK=0x0
FAULT_MODEL=RUNTIME
[FIU16]
NET_NAME=a
LFSR_MASK=0x0
FAULT_MODEL=RUNTIME
[FIU28]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x0
[FIU9]
NET_NAME=a
LFSR_MASK=0xa
FAULT_MODEL=RUNTIME
[FIU6]
NET_NAME=a
LFSR_MASK=0x7
FAULT_MODEL=RUNTIME
[FIU18]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x0
[FIU8]
NET_NAME=a
LFSR_MASK=0x9
FAULT_MODEL=RUNTIME
[FIU3]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x4
[FIU15]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x10
[FIU10]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0xb
[FIU12]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0xd
[FIU2]
NET_NAME=a
LFSR_MASK=0x3
FAULT_MODEL=RUNTIME
[FIU4]
NET_NAME=a
LFSR_MASK=0x5
FAULT_MODEL=RUNTIME
[FIU30]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x0
[FIU23]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x0
[FIU22]
NET_NAME=a
LFSR_MASK=0x0
FAULT_MODEL=RUNTIME
[FIU13]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0xe
[FIU5]
NET_NAME=a
LFSR_MASK=0x6
FAULT_MODEL=RUNTIME
[FIU14]
NET_NAME=a
LFSR_MASK=0xf
FAULT_MODEL=RUNTIME
[FIU26]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x0
[FIU0]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x1
[FIU1]
NET_NAME=a
LFSR_MASK=0x2
FAULT_MODEL=RUNTIME
[FIU25]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x0
[FIU19]
NET_NAME=a
LFSR_MASK=0x0
FAULT_MODEL=RUNTIME
[FIU11]
NET_NAME=a
LFSR_MASK=0xc
FAULT_MODEL=RUNTIME
[FIU27]
NET_NAME=a
LFSR_MASK=0x0
FAULT_MODEL=RUNTIME
[FIU17]
FAULT_MODEL=RUNTIME
[FIU1]
NET_NAME=a
LFSR_MASK=0x0
[FIU7]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x8
[CONSTS]
LFSR_WIDTH=16
......@@ -153,7 +18,7 @@ TRIGGER_EXT_EN=0
LFSR_POLY=0x2d
BAUDRATE=115200
FREQUENCY=20000000
FIU_NUM=32
FIU_NUM=2
RESET_EXT_EN=0
TIMER_WIDTH=32
RESET_DUT_OUT_EN=0
......@@ -163,19 +28,3 @@ FIU_CFG_BITS=3
RESET_DUT_IN_EN=0
ID=0x0123
[FIU24]
NET_NAME=a
LFSR_MASK=0x0
FAULT_MODEL=RUNTIME
[FIU20]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x0
[FIU29]
FAULT_MODEL=RUNTIME
NET_NAME=a
LFSR_MASK=0x0
## @file
use strict;
use warnings;
use Log::Log4perl qw(get_logger);
use FIJI::Connection;
use FIJI::Settings;
sub test_fi_uart {
my ($port, $payload_ref, $t1_duration, $t2_duration, $trigger_en, $trigger_ext, $reset, $fiji_consts) = @_;
# my @payload = map hex($_), $cfg_str =~ /(..)/g; # TODO: how to do this with unpack?
my %config = (
payload => $payload_ref,
t1_duration => $t1_duration,
t2_duration => $t2_duration,
trigger_en => $trigger_en,
trigger_ext => $trigger_ext,
reset => $reset,
consts => $fiji_consts,
);
$port->send_config(\%config, 1000, 0, 1);
}
sub main {
my @ARGV = @_;
my $logger = get_logger();
my $name = $0;
$name =~ s/\.p[lm]//;
my $cfgname = $name . ".cfg";
$logger->debug("=== Starting new execution of $name ===");
$logger->debug(sprintf("%d argument(s)%s", scalar(@_), scalar(@_) > 0 ? ": @_" : ""));
my $fiji_settings = FIJI::Settings->new('download', $ARGV[0]);
if (!ref($fiji_settings)) {
printf($fiji_settings . " Aborting.\n");
return 1;
}
my $fiji_consts = $fiji_settings->{'design'};
my $fius = $fiji_settings->{'FIUs'};
my $lfsr_fmt = sprintf("X\"%%0%dx\"",$fiji_consts->{'LFSR_WIDTH'}/4);
my @fiu_configs = ();
for (my $i = 0; $i < $fiji_consts->{'FIU_NUM'}; $i++) {
my $lfsr_mask = sprintf("$lfsr_fmt",@{$fius}[$i]->{'FIU_LFSR_MASK'});
my $str =<<"END_FIU";
$i => (
fault_model => @{$fius}[$i]->{'FIU_MODEL'},
lfsr_mask => $lfsr_mask
)
END_FIU
push @fiu_configs,$str;
}
my $lfsr_poly_string = sprintf($lfsr_fmt,$fiji_consts->{'LFSR_POLY'});
my $lfsr_seed_string = sprintf($lfsr_fmt,$fiji_consts->{'LFSR_SEED'});
my $fault_detect_string = "00";
my $fiu_configs_string = join(" ,\n",@fiu_configs);
my $vhdl =<<"END_VHDL";
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.fault_selection_type_pkg.all;
package public_config_pkg is
------------------------------------------------------------------------------
-- Design configuration
------------------------------------------------------------------------------
-- The design's clock frequency
constant c_frequency : positive := $fiji_consts->{'FREQUENCY'};
-- The baud rate
constant c_baudrate : positive := $fiji_consts->{'BAUDRATE'};
-- The invert mask for the fault detection signals
constant c_fault_detect_invert_mask : std_logic_vector(1 downto 0) := $fault_detect_string;
------------------------------------------------------------------------------
-- LFSR configuration
------------------------------------------------------------------------------
-- Width of the LFSR for random FIU enable & stuck-open
constant c_lfsr_width : natural := $fiji_consts->{'LFSR_WIDTH'};
-- Polynomial for the LFSR
constant c_lfsr_poly : std_logic_vector(c_lfsr_width-1 downto 0) := $lfsr_poly_string;
-- Initial value for the LFSR
constant c_lfsr_seed : std_logic_vector(c_lfsr_width-1 downto 0) := $lfsr_seed_string;
------------------------------------------------------------------------------
-- Controller Configuration
------------------------------------------------------------------------------
-- Width of the timers in bytes.
constant c_timer_width : natural := $fiji_consts->{'TIMER_WIDTH'};
-- FIC -> DUT reset signal: active level
constant c_reset_dut_in_active : std_logic := '0';
-- reset duration
constant c_reset_dut_in_duration : positive := 4;
-- external reset signal: active level
constant c_reset_ext_active : std_logic := '0';
-- DUT -> FIC reset signal: active level
constant c_reset_dut_out_active : std_logic := '0';
-- active level of the external and internal triggers
constant c_trigger_ext_active : std_logic := '0';
constant c_trigger_dut_active : std_logic := '1';
-- hardware id
constant c_id : std_logic_vector(15 downto 0) := X"0123";
------------------------------------------------------------------------------
-- FIU Configuration
------------------------------------------------------------------------------
type t_single_fiu_record is record
fault_model : t_select_fault_models; --Select dynamic or single fault model. See fault_injection_unit
lfsr_mask : std_logic_vector(c_lfsr_width-1 downto 0); -- Select which LFSR bits to AND for Stuck-open fault
end record t_single_fiu_record;
type t_fiu_records is array (natural range <>) of t_single_fiu_record;
constant c_fiu_config : t_fiu_records := (
$fiu_configs_string
);
end package public_config_pkg;
END_VHDL
print $vhdl;
$logger->trace("=== Stopping execution ===");
return 0;
}
Log::Log4perl::init_and_watch('logger.conf', 'HUP');
exit main(@ARGV);
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