Commit f461c510 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Extend TRM

parent 0551936b
\acro{LOC}{Lines Of Code}
\acro{FIJI}{Fault InJection Instrumenter}
\acro{FIU}{Fault Injection Unit}
\acro{SEU}{Single Event Upset}
\acro{FIC}{Fault Injection Controller}
\acro{DUT}{Design under Test}
\acro{UART}{Universal Asynchronous Receiver Transmitter}
......
......@@ -41,3 +41,24 @@ configurations or even fault patterns themselves without a gap. If the new
configuration does not arrive in time, the FIC notifies the host by sending
\textit{UNDERRUN}. It then waits for a new configuration to be downloaded.
\subsection{Fault Models}
The \acp{FIU} can be configured to forward the following signal types:
\begin{itemize}
\item Original signal (no fault)
\item Stuck at 0 level
\item Stuck at 1 level
\item Original signal delayed by one clock (delay fault)
\item Inversion of the original signal for a single clock cycle (\ac{SEU})
\item Pseudo-random data (stuck-open)
\end{itemize}
An overview of the effects of each fault model can be seen in Figure~\ref{fig:faulttiming}.
\begin{figure}[ht]
\centering
\input{img/fault_modes.tex}
\caption{Timing Diagrams for Fault Models}
\label{fig:faulttiming}
\end{figure}
\begin{tabular}{lllp{25em}}
\toprule
Name & Range & Default & Description\\
\midrule
CLOCK\_NET & String & -- & Name of the clock net in the DUT to be used for clocking the \ac{FIJI} logic\\
FREQUENCY & Design-dependent & 5.00E+07 & Clock frequency of CLOCK\_NET in Hertz\\
BAUDRATE & Host-dependent & 115200 & Baud rate of the serial connection between host and DUT\\
ID & 0 to $2^{16}-1$ & Automatic hash & Design ID\\
TIMER\_WIDTH & 1 to 64 & 32 & Width in bytes of the timer\\
LFSR\_WIDTH & 1 to 64 & 16 & Width in bits of the shared \ac{LFSR}\\
LFSR\_POLY & 0 to $2^{\text{LFSR\_WIDTH}}$-1 & 0x2D & Polynomial specifying the \ac{LFSR} architecture\\
LFSR\_SEED & 0 to $2^{\text{LFSR\_WIDTH}}$-1 & 0xCAFE & Polynomial specifying the \ac{LFSR} architecture\\
FAULT\_DETECT\_INVERT\_MASK & 0 to 3 & 0 & Invert fault detection nets\\
RESET\_EXT\_EN & 0 to 1 & 0 & Enable flag for the external reset input for \ac{FIJI}\\
RESET\_EXT\_ACTIVE & 0 to 1 & -- & Active level of the external reset input\\
RESET\_DUT\_OUT\_EN & 0 to 1 & 0 & Enable flag for the reset from the DUT to \ac{FIJI}\\
RESET\_DUT\_OUT\_NAME & String & -- & Name of the net in the DUT that should drive \ac{FIJI}’s reset (if any)\\
RESET\_DUT\_OUT\_ACTIVE & 0 to 1 & -- & Active level of RESET\_DUT\_OUT\_NAME\\
RESET\_DUT\_IN\_EN & 0 to 1 & 0 & Enable flag for the reset from \ac{FIJI} to the DUT\\
RESET\_DUT\_IN\_NAME & String & -- & Name of the reset net in the DUT to be driven by \ac{FIJI} (if any)\\
RESET\_DUT\_IN\_DURATION & 1 to $2^{32}-1$ & -- & Duration of RESET\_DUT\_IN\_NAME in clock cycles\\
RESET\_DUT\_IN\_ACTIVE & 0 to 1 & -- & Active level of RESET\_DUT\_IN\_NAME\\
TRIGGER\_DUT\_EN & 0 to 1 & 0 & Enable flag for the trigger from the DUT to \ac{FIJI}\\
TRIGGER\_DUT\_NAME & String & -- & Name of the net in the DUT to be used as an internal trigger for \ac{FIJI}\\
TRIGGER\_DUT\_ACTIVE & 0 to 1 & -- & Active level of TRIGGER\_DUT\_NAME\\
TRIGGER\_EXT\_EN & 0 to 1 & 0 & Enable flag for the external trigger input for \ac{FIJI}\\
TRIGGER\_EXT\_ACTIVE & 0 to 1 & -- & Active level of the external trigger input\\
\bottomrule
\end{tabular}
\ No newline at end of file
\begin{tabular}{ll}
\toprule
Literal & Description \\
\midrule
RUNTIME & All fault models are available at runtime (to be selected via \ac{FIU} config) \\
STUCK\_AT\_0 & Only stuck-at-0 is available as fault model. \ac{FIU} configurations other than ``001'' lead to pass-thru behavior. \\
STUCK\_AT\_1 & Only stuck-at-1 is available as fault model. \ac{FIU} configurations other than ``010'' lead to pass-thru behavior. \\
DELAY & Only delay fault is available as fault model. \ac{FIU} configurations other than ``011'' lead to pass-thru behavior. \\
SEU & Only SEU is available as fault model. \ac{FIU} configurations other than ``100'' lead to pass-thru behavior. \\
STUCK\_OPEN & Only stuck-open is available as fault model. \ac{FIU} configurations other than ``101'' lead to pass-thru behavior. \\
PASS\_THRU & \ac{FIU} always passes through the original signal \\
\bottomrule
\end{tabular}
\begin{tabular}{llll}
\toprule
Name & Range & Default & Description\\
\midrule
NET\_NAME & Existing Verilog net & -- & The Verilog net the FIU is connected with. \\
FAULT\_MODEL & RUNTIME etc., cf Table~\ref{tab:faultmodels} & RUNTIME & The fault model(s) the \ac{FIU} should implement \\
LFSR\_MASK & 0 to $2^{\text{LFSR\_WIDTH}} - 1$ & 0 & \ac{LFSR} bits selected by this mask are ANDed as input for stuck-open output \\
\bottomrule
\end{tabular}
\ No newline at end of file
\begin{tabular}{lll}
\toprule
Name & Type & Description \\
\midrule
c\_baudrate & positive & Baud rate (e.g., 9600, 115200, \ldots) \\
c\_fiu\_config & t\_fiu\_records & Configuration of fault model \& LFSR settings for each FIU \\
c\_frequency & positive & System clock frequency in Hz (e.g., 50000000) \\
c\_id & std\_logic\_vector(15 downto 0) & \ac{FIJI} Hardware ID \\
c\_lfsr\_poly & std\_logic\_vector(c\_lfsr\_width-1 downto 0) & Polynomial for the \ac{LFSR} \\
c\_lfsr\_seed & std\_logic\_vector(c\_lfsr\_width-1 downto 0) & Initial value for the \ac{LFSR} \\
c\_lfsr\_width & positive & Width of the \ac{LFSR} for stuck-open \\
c\_reset\_dut\_in\_active & std\_logic & \ac{DUT} $\rightarrow$ \ac{FIC} reset signal: active level \\
c\_reset\_dut\_in\_duration & positive & \ac{FIC} $\rightarrow$ \ac{DUT} reset signal: active duration \\
c\_reset\_dut\_out\_active & std\_logic & \ac{FIC} $\rightarrow$ \ac{DUT} reset signal: active level \\
c\_reset\_ext\_active & std\_logic & External reset signal: active level \\
c\_timer\_width & positive & Width of the timer in bytes \\
c\_trigger\_dut\_active & std\_logic & Active level of the internal trigger \\
c\_trigger\_ext\_active & std\_logic & Active level of the external trigger \\
\bottomrule
\end{tabular}
\begin{tabular}{lll}
\toprule
Name & Description \\
\midrule
Log::Log4perl & Logging framework \\
Win32::SerialPort & Serial port interface for Windows \\
Device::SerialPort & Serial port interface for Unix \\
Scalar::Util & Various numeric helpers \\
Config::Simple & Configuration file handling \\
Switch & Switch construct \\
Digest::CRC & CRC calculation \\
Time::HiRes & High-resolution timing \\
Doxygen::Filter::Perl & Perl support for Doxygen documentation \\
\bottomrule
\end{tabular}
\begin{tabular}{lll}
\toprule
Name & Type & Description \\
\midrule
s\_fiji\_clk\_i & std\_logic & System clock \\
s\_fiji\_reset\_ext\_i & std\_logic & External asynchronous reset \\
s\_fiji\_reset\_dut\_out\_i & std\_logic & Internal reset DUT $\rightarrow$ FIC \\
s\_fiji\_rx\_i & std\_logic & Serial in \\
s\_fiji\_trigger\_ext\_i & std\_logic & External trigger input (assumed asynchronous) \\
s\_fiji\_trigger\_dut\_i & std\_logic & Trigger input from DUT (assumed synchronous) \\
s\_fiji\_original\_i & std\_logic\_vector(c\_fiu\_config'length-1 downto 0) & Original nets \\
\bottomrule
\end{tabular}
\begin{tabular}{lll}
\toprule
Name & Type & Description \\
\midrule
s\_fiji\_reset\_dut\_out\_o & std\_logic & Internal reset FIC $\rightarrow$ DUT \\
s\_fiji\_rx\_i & std\_logic & Serial out \\
s\_fiji\_modified\_o & std\_logic\_vector(c\_fiu\_config'length-1 downto 0) & Modified nets \\
\bottomrule
\end{tabular}
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