Commit f3378e01 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Test export as VHDL architecture small fix

fixed invalid comparison and unnecessary print
parent 63f12c9f
...@@ -58,7 +58,7 @@ END_CLKCNTR ...@@ -58,7 +58,7 @@ END_CLKCNTR
$vhdl .= sprintf("--trigger synchronization/edge detection\n".$clkcntr, 2); $vhdl .= sprintf("--trigger synchronization/edge detection\n".$clkcntr, 2);
} }
if (defined $reset && $reset != 0) { if (defined $reset && $reset ne 0) {
$vhdl .= $indent."-- BEGIN reset time ($settings_ref->{'design'}->{'RST_DUT_IN_DUR'})\n"; $vhdl .= $indent."-- BEGIN reset time ($settings_ref->{'design'}->{'RST_DUT_IN_DUR'})\n";
# $vhdl .= $indent."wait for ".(($settings_ref->{'design'}->{'RST_DUT_IN_DUR'})*$period)." $si;\n"; # $vhdl .= $indent."wait for ".(($settings_ref->{'design'}->{'RST_DUT_IN_DUR'})*$period)." $si;\n";
$vhdl .= sprintf($clkcntr, $settings_ref->{'design'}->{'RST_DUT_IN_DUR'}) $vhdl .= sprintf($clkcntr, $settings_ref->{'design'}->{'RST_DUT_IN_DUR'})
...@@ -302,7 +302,6 @@ sub export_as_vhd_fiji_architecture { ...@@ -302,7 +302,6 @@ sub export_as_vhd_fiji_architecture {
my $lfsr_width_multiple_of_4 = ceil($design_ref->{'LFSR_WIDTH'}/4)*4-1; my $lfsr_width_multiple_of_4 = ceil($design_ref->{'LFSR_WIDTH'}/4)*4-1;
my $lfsr_fmt = "\%0".ceil($design_ref->{'LFSR_WIDTH'}/4)."X"; my $lfsr_fmt = "\%0".ceil($design_ref->{'LFSR_WIDTH'}/4)."X";
print "============== $lfsr_fmt =================";
my $lfsr_seed_hex = sprintf($lfsr_fmt,$design_ref->{'LFSR_SEED'}); my $lfsr_seed_hex = sprintf($lfsr_fmt,$design_ref->{'LFSR_SEED'});
my $lfsr_poly_hex = sprintf($lfsr_fmt,$design_ref->{'LFSR_POLY'}); my $lfsr_poly_hex = sprintf($lfsr_fmt,$design_ref->{'LFSR_POLY'});
...@@ -607,4 +606,4 @@ END_VHDL ...@@ -607,4 +606,4 @@ END_VHDL
return $msg; return $msg;
} }
1; 1;
\ No newline at end of file
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