Skip to content
GitLab
Projects
Groups
Snippets
/
Help
Help
Support
Community forum
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
Menu
Open sidebar
vecs
FIJI Public
Commits
f00fddc2
Commit
f00fddc2
authored
Jun 21, 2017
by
Christian Fibich
Committed by
Stefan Tauner
May 04, 2018
Browse files
Remove Synplify resources synthesis project
Addresses issue vecs/fiji#54
parent
5382a9be
Changes
1
Hide whitespace changes
Inline
Side-by-side
hw/impl/Synplify/device_resources.prj
deleted
100644 → 0
View file @
5382a9be
#-- Synopsys, Inc.
#-- Version I-2013.09-SP1
#-- Project file /home/fibich/git/fiji-internal/hw/impl/Synplify/device_resources.prj
#project files
add_file -vhdl -lib work "../fiji/fiji_config_pkg.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_controller_.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_controller_pkg.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_controller_rtl.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_top_.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_top_pkg.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_top_struc.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_tx_buffer_.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_tx_buffer_pkg.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_tx_buffer_rtl.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_uart_.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_uart_pkg.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_uart_rtl.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_unit_.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_unit_pkg.vhd"
add_file -vhdl -lib work "../../rtl/fault_injection_unit_rtl.vhd"
add_file -vhdl -lib work "../../rtl/fault_selection_type_pkg.vhd"
add_file -vhdl -lib work "../../rtl/private_config_pkg.vhd"
#implementation: "ArriaII"
impl -add ArriaII -type fpga
#device options
set_option -technology ARRIAII-GX
set_option -part EP2AGX260F
set_option -package FC35
set_option -speed_grade -6
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# altera_options
set_option -RWCheckOnRam 1
# mapper_options
set_option -frequency auto
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# Altera STRATIX
set_option -run_prop_extract 1
set_option -maxfan 30
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
set_option -quartus_version 13.1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./ArriaII/arriaii.vqm"
#implementation: "StratixIII"
impl -add StratixIII -type fpga
#device options
set_option -technology STRATIXIII
set_option -part EP3SL70
set_option -package FC484
set_option -speed_grade -2
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# altera_options
set_option -RWCheckOnRam 1
# mapper_options
set_option -frequency auto
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# Altera STRATIX
set_option -run_prop_extract 1
set_option -maxfan 30
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
set_option -quartus_version 13.1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./StratixIII/stratixiii.vqm"
#implementation: "CycloneIIILS"
impl -add CycloneIIILS -type fpga
#device options
set_option -technology CYCLONEIII-LS
set_option -part EP3CLS200
set_option -package FC484
set_option -speed_grade -7
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# altera_options
set_option -RWCheckOnRam 1
# mapper_options
set_option -frequency auto
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# Altera STRATIX
set_option -run_prop_extract 1
set_option -maxfan 30
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
set_option -quartus_version 13.1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./CycloneIIILS/cycloneiiils.vqm"
#implementation: "CycloneV"
impl -add CycloneV -type fpga
#device options
set_option -technology CYCLONEV
set_option -part 5CSXFC6C6
set_option -package UA23
set_option -speed_grade -7
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# altera_options
set_option -RWCheckOnRam 1
# mapper_options
set_option -frequency auto
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# Altera STRATIX
set_option -run_prop_extract 1
set_option -maxfan 30
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
set_option -quartus_version 13.1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./CycloneV/cyclonev.vqm"
#implementation: "StratixV"
impl -add StratixV -type fpga
#device options
set_option -technology STRATIXV
set_option -part 5SGTMC5K3
set_option -package FC40
set_option -speed_grade -2
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# altera_options
set_option -RWCheckOnRam 1
# mapper_options
set_option -frequency auto
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# Altera STRATIX
set_option -run_prop_extract 1
set_option -maxfan 30
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
set_option -quartus_version 13.1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./StratixV/stratixv.vqm"
#implementation: "Virtex5"
impl -add Virtex5 -type fpga
#device options
set_option -technology Virtex5
set_option -part XC5VLX20T
set_option -package FF323
set_option -speed_grade -2
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# mapper_options
set_option -frequency auto
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# xilinx_options
set_option -RWCheckOnRam 1
# Xilinx Virtex2
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
# Xilinx Virtex5
set_option -enable_prepacking 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./Virtex5/virtex5.edf"
#implementation: "Zync7020"
impl -add Zync7020 -type fpga
#device options
set_option -technology Zynq
set_option -part XC7Z020
set_option -package CLG400
set_option -speed_grade -2
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# mapper_options
set_option -frequency auto
set_option -write_verilog 1
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# xilinx_options
set_option -RWCheckOnRam 1
# Xilinx Virtex2
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
# Xilinx Zynq
set_option -use_vivado 0
set_option -enable_prepacking 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./Zync7020/zync7020.edf"
#implementation: "Spartan6"
impl -add Spartan6 -type fpga
#device options
set_option -technology Spartan6
set_option -part XC6SLX9
set_option -package CSG225
set_option -speed_grade -2
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# mapper_options
set_option -frequency auto
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# xilinx_options
set_option -RWCheckOnRam 1
# Xilinx Spartan3
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -retiming 0
set_option -update_models_cp 0
set_option -fix_gated_and_generated_clocks 1
set_option -no_sequential_opt 0
# Xilinx Spartan6
set_option -enable_prepacking 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./Spartan6/spartan6.edf"
#implementation: "Kintex7"
impl -add Kintex7 -type fpga
#device options
set_option -technology Kintex7
set_option -part XC7K70T
set_option -package FBG676
set_option -speed_grade -2
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# mapper_options
set_option -frequency auto
set_option -write_verilog 1
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# xilinx_options
set_option -RWCheckOnRam 1
# Xilinx Virtex2
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
# Xilinx Kintex7
set_option -use_vivado 1
set_option -enable_prepacking 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./Kintex7/kintex7.edf"
#implementation: "Artix7"
impl -add Artix7 -type fpga
#device options
set_option -technology Artix7
set_option -part XC7A100T
set_option -package CSG324
set_option -speed_grade -1
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# mapper_options
set_option -frequency auto
set_option -write_verilog 1
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# xilinx_options
set_option -RWCheckOnRam 1
# Xilinx Virtex2
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
# Xilinx Artix7
set_option -use_vivado 1
set_option -enable_prepacking 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./Artix7/artix7.edf"
impl -active "Artix7"
Write
Preview
Supports
Markdown
0%
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment