DE0 Demo

Added template qsf for FIJI pin constraints
Added FIU names
Added connection figure to user manual section

docs/demos/tmr_vga/fiji/de0_test_1/fiji/fiji.cfg

 ; FIJI::ConfigSorted 0.1
-; Thu Aug 18 12:58:07 2016
+; Thu Sep  7 16:29:46 2017
 
 [CONSTS]
 BAUDRATE=115200
@@ -24,6 +24,7 @@ OUTPUT_DIR=.
 RST_DUT_IN_ACT=1
 RST_DUT_IN_DUR=1
 RST_DUT_IN_EN=0
+RST_DUT_IN_NAME=
 RST_DUT_OUT_ACT=0
 RST_DUT_OUT_EN=1
 RST_DUT_OUT_NAME="spriteflyer_top/s_reset_n_c"
@@ -46,6 +47,7 @@ DRIVER_PATH="\\spriteflyer_sprite_generate_tmr_partitions.0.i_sprite_0 /s_sprite
 DRIVER_TYPE=PIN
 FAULT_MODEL=RUNTIME
 LFSR_MASK=0x1
+NAME=Sprite Line
 NET_NAME="spriteflyer_top/generate_tmr_partitions_0_i_sprite/s_sprite_line[0]"
 
 [FIU1]
@@ -53,6 +55,7 @@ DRIVER_PATH="\\spriteflyer_sprite_generate_tmr_partitions.0.i_sprite_0 /s_x_stat
 DRIVER_TYPE=PIN
 FAULT_MODEL=RUNTIME
 LFSR_MASK=0x2
+NAME=X State
 NET_NAME="spriteflyer_top/generate_tmr_partitions_0_i_sprite/s_x_state"
 
 [FIU2]
@@ -60,6 +63,7 @@ DRIVER_PATH="spriteflyer_top/generate_tmr_partitions_0_i_sprite/s_green_o"
 DRIVER_TYPE=PIN
 FAULT_MODEL=RUNTIME
 LFSR_MASK=0x4
+NAME=Green
 NET_NAME="spriteflyer_top/s_green_tmr_partitions[3]"
 
 

docs/demos/tmr_vga/fiji/de0_test_1/quartus/fiji_pins.qsf

+set_location_assignment PIN_G3 -to s_fiji_trig_ext_i
+set_location_assignment PIN_V6 -to s_fiji_tx_o
+set_location_assignment PIN_V7 -to s_fiji_rx_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_fiji_rx_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_fiji_trig_ext_i
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_fiji_tx_o
+set_instance_assignment -name SLEW_RATE 2 -to s_fiji_tx_o
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_fiji_tx_o
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_fiji_rx_i
+set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_fiji_trig_ext_i

docs/user_guide/content/08-demo.tex

@@ -85,8 +85,13 @@ In a real-world design the states of the redundant units would usually be determ
 \end{itemize}
 
 \subsubsection{Terasic DE0}
+
 \begin{itemize}
     \item Connect a 3V3 Serial TTL cable to the DE0:
+
+        \begin{minipage}[h]{\linewidth}
+        \centering
+        \begin{minipage}{0.45\linewidth}
         \begin{itemize}
             \item Connect \textit{Ground} to any GND pin on GPIO1 (e.g., J5.30).
             \item Connect \textit{TXD (Host-to-Device)} to GPIO1\_D31 (J5.40).
@@ -96,11 +101,25 @@ In a real-world design the states of the redundant units would usually be determ
             \item If your cable requires an I/O voltage input (e.g., FTDI TTL-232R-VIP),
                   connect the correspondig wire to any 3V3 pin on GPIO1 (e.g., J5.29).
         \end{itemize}
+        \end{minipage}
+        \hspace{0.05\linewidth}
+        \begin{minipage}{0.45\linewidth}
+        \begin{figure}[H]
+        \centering
+        \includegraphics[height=20em]{img/de0_j5.pdf}
+        \caption{DE0 Connections}
+        \label{fig:de0_connections}
+        \end{figure}
+        \end{minipage}
+
+    \end{minipage}
+    \vspace{1em}
+
     \item Connect a VGA-compatible monitor to the VGA port.
           The design generates a 640x480 @ 25Mhz VGA signal.
     \item The dip-switch SW0 controls if TMR is enabled (towards the board edge is off).
     \item BUTTON0 resets the design.
-    % FIXME: External Trigger
+    \item The external trigger is activated when BUTTON1 is pressed.
     \item The green LEDs above the three buttons (LEDG0-LEDG3) show the error detection state:
         \begin{itemize}
             \item LEDG0 shows if any error has been detected.