Commit e1bcf469 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Fixed unused wire in multipin testcase

parent 6f39649a
; FIJI::ConfigSorted 0.1
; Tue Mar 29 16:41:57 2016
; Thu Mar 31 16:06:19 2016
[CONSTS]
BAUDRATE=115200
......
......@@ -19,6 +19,14 @@ endmodule
`endif
module my_and (a, b, y);
input a;
input b;
output y;
assign y = a & b;
endmodule;
module top (
i, o, clk
);
......@@ -26,10 +34,13 @@ input clk;
input i;
output o;
wire [1:0] bus;
wire wa, wb;
carry_sum cell1 (.sin(i), .cin(i), .sout(bus[0]), .cout(bus[1]));
assign o = bus[0];
my_and cell2 (.a(wa),.b(wb),.y(o));
assign wa = bus[0];
assign wb = bus[1];
endmodule
\ No newline at end of file
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