Commit df4f0a99 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Refine user manual

Describe makefile in TMR Demo
Fix Zybo PMOD figure
Update http links
Fix #s in EE CLI listing
parent 1662ea7c
...@@ -179,7 +179,7 @@ To choosen between the various fault models one has to enter its index. ...@@ -179,7 +179,7 @@ To choosen between the various fault models one has to enter its index.
The mapping between these fault indices and the respective fault models is shown in \Cref{tab:faultmap}. The mapping between these fault indices and the respective fault models is shown in \Cref{tab:faultmap}.
\begin{figure} \begin{figure}
\begin{lstlisting}[caption=Interactive configuration session,label=lst:manualprompt,style=plain] \begin{lstlisting}[caption=Interactive configuration session,label=lst:manualprompt,style=plain,commentstyle=]
Enter configuration for FIU #0 in t2 (default: 0x7): 0 Enter configuration for FIU #0 in t2 (default: 0x7): 0
Enter configuration for FIU #0 after t2 (default: 0x7): 1 Enter configuration for FIU #0 after t2 (default: 0x7): 1
Enter configuration for FIU #1 in t2 (default: 0x7): 2 Enter configuration for FIU #1 in t2 (default: 0x7): 2
......
...@@ -18,9 +18,9 @@ engine can be seen on the right side. ...@@ -18,9 +18,9 @@ engine can be seen on the right side.
\end{figure} \end{figure}
The use case is designated for use with the Cyclone III-based DE0 development The use case is designated for use with the Cyclone III-based DE0 development
board from Terasic\footnote{\url{http://de0.terasic.com.tw}, visited on August~29, 2016}, board from Terasic\footnote{\url{http://de0.terasic.com.tw}, visited on May~7, 2018},
the Artix~7-based Basys~3\footnote{\url{https://reference.digilentinc.com/reference/programmable-logic/basys-3/start}, visited on April~12, 2017}, the Artix~7-based Basys~3\footnote{\url{https://reference.digilentinc.com/reference/programmable-logic/basys-3/start}, visited on May~7, 2017},
or the Zynq~7000-based Zybo\footnote{\url{https://reference.digilentinc.com/reference/programmable-logic/zybo/start}, visited on April~12, 2017}, or the Zynq~7000-based Zybo\footnote{\url{https://reference.digilentinc.com/reference/programmable-logic/zybo/start}, visited on May~7, 2017},
but is portable to other boards providing a \ac{VGA} connector with little effort. It is implemented in VHDL. but is portable to other boards providing a \ac{VGA} connector with little effort. It is implemented in VHDL.
\begin{figure}[htb] \begin{figure}[htb]
...@@ -149,6 +149,9 @@ Due to the various supported boards there are some important points to consider ...@@ -149,6 +149,9 @@ Due to the various supported boards there are some important points to consider
To reconstruct the execution of the flow to configure, instrument and synthesize the design with injection logic, the following steps have to be executed. To reconstruct the execution of the flow to configure, instrument and synthesize the design with injection logic, the following steps have to be executed.
The makefile found in \texttt{<FIJI ROOT>/docs/demos/tmr\_vga} optionally guides the user through the \ac{FIJI} flow, executing the following steps
in a partly automatized manner, providing information about each step. To use this makefile, execute \texttt{make} in the demo directory.
\subsubsection{Input Netlist} \subsubsection{Input Netlist}
The steps hereinafter assume that you have already synthesized a netlist of the original design with Synopsis Synplify. The steps hereinafter assume that you have already synthesized a netlist of the original design with Synopsis Synplify.
...@@ -175,7 +178,7 @@ The resulting file should be located in the \texttt{synp} directory (e.g., \text ...@@ -175,7 +178,7 @@ The resulting file should be located in the \texttt{synp} directory (e.g., \text
\subsubsection{Synthesis using Synplify Pro} \subsubsection{Synthesis using Synplify Pro}
\begin{enumerate} \begin{enumerate}
\item Create a new Synplify project file named 'spriteflyer\_top.prj' in \texttt{fiji/de0\_test\_1/synp} \item Create a new Synplify project file named ``spriteflyer\_top.prj'' in \texttt{fiji/de0\_test\_1/synp}
\item Open the project \item Open the project
\item Rename the (default) implementation to \texttt{basys3}, \texttt{de0}, \texttt{zybo}, etc. respectively. \item Rename the (default) implementation to \texttt{basys3}, \texttt{de0}, \texttt{zybo}, etc. respectively.
......
\section{Yosys Demonstration with \texttt{tinyvga}} \section{Yosys Demonstration with \texttt{tinyvga}}
Another demo design was implemented in Verilog in order to demonstrate the Another demo design was implemented in Verilog in order to demonstrate the
interoperability with the open-source synthesis framework Yosys\footnote{\url{http://www.clifford.at/yosys/},~visited on September 14, 2017} interoperability with the open-source synthesis framework Yosys\footnote{\url{http://www.clifford.at/yosys/},~visited on May~7, 2018}
and the IceStorm toolchain\footnote{\url{http://www.clifford.at/icestorm/},~visited on September 14, 2017}. and the IceStorm toolchain\footnote{\url{http://www.clifford.at/icestorm/},~visited on May~7, 2018}.
The target board for this design is the \emph{HX8K Breakout Board}\footnote{\url{http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx},~visited on September 14, 2017} The target board for this design is the \emph{HX8K Breakout Board}\footnote{\url{http://www.latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx},~visited on May~7, 2018}
offered by Lattice Semiconductor Corp. Additionally, a VGA DAC extension offered by Lattice Semiconductor Corp. Additionally, a VGA DAC extension
board such as the XESS StickIt VGA module\footnote{\url{http://www.xess.com/shop/product/stickit-vga/},~visited on September 14, 2017} is needed. board such as the XESS StickIt VGA module\footnote{\url{http://www.xess.com/shop/product/stickit-vga/},~visited on May~7, 2018} is needed.
The design generates SVGA ($800\times600$ pixels, $3\times4$ bits of color) output with 36\;MHz pixel clock generated The design generates SVGA ($800\times600$ pixels, $3\times4$ bits of color) output with 36\;MHz pixel clock generated
by an iCE40 PLL from the 12\;MHz on-board oscillator. It moves the content by an iCE40 PLL from the 12\;MHz on-board oscillator. It moves the content
......
...@@ -14,7 +14,7 @@ ...@@ -14,7 +14,7 @@
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...@@ -102,8 +102,8 @@ ...@@ -102,8 +102,8 @@
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...@@ -236,7 +236,7 @@ ...@@ -236,7 +236,7 @@
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