Commit c277e393 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Documented HX8K demo in the user manual

parent 037197bf
......@@ -21,7 +21,7 @@ The use case is designated for use with the Cyclone III-based DE0 development
board from Terasic\footnote{\url{}, visited on August~29, 2016},
the Artix~7-based Basys~3\footnote{\url{}, visited on April~12, 2017},
or the Zynq~7000-based Zybo\footnote{\url{}, visited on April~12, 2017},
but is portable to other boards providing a \ac{VGA} connector with little effort.
but is portable to other boards providing a \ac{VGA} connector with little effort. It is implemented in VHDL.
......@@ -154,7 +154,7 @@ To reconstruct the execution of the flow to configure, instrument and synthesize
The steps hereinafter assume that you have already synthesized a netlist of the original design with Synopsis Synplify.
A suitable Synopsis project and constraint file is provided in \texttt{synp/de0/}.
Synthesizing this with Synplify creates a netlist compatible to our tool (or more specifically to Verilog-Perl).
The resulting file should be located in the \texttt{synp} directory (e.g., synp/de0/de0/spriteflyer\_top.vqm).
The resulting file should be located in the \texttt{synp} directory (e.g., \texttt{synp/de0/de0/spriteflyer\_top.vqm}).
\subsubsection{Run setup}
A pre-configured settings file for \ac{FIJI} is located in \texttt{fiji/de0\_test\_1/fiji/fiji.cfg}.
......@@ -325,3 +325,112 @@ generated by majority voting over the three \ac{TMR} domains. Faults in \ac{TMR}
domain 0 are masked and thus are not visible. When \ac{TMR} is enabled, the LEDs on
the board show (1) if an error is detected by the voter (one domain disagrees
with the others) and (2) in which voter (Red, Green, Blue) the error is detected.
\section{Yosys Demo}
Another demo design was implemented in Verilog in order todemonstrate the
interoperability with the open-source synthesis framework Yosys~\footnote{,~visited on September 14, 2017}
and the IceStorm toolchain~\footnote{,~visited on September 14, 2017}.
The target board for this design is the \emph{HX8K Breakout Board}~\footnote{,~visited on September 14, 2017}
offered by Lattice Semiconductor Corp. Additionally, a VGA DAC extension
board such as the XESS StickIt VGA module~\footnote{,~visited on September 14, 2017} is needed.
The design generates SVGA 800x600 output with 36~MHz pixel clock generated
by an iCE40 PLL from the 12~MHz on-board oscillator. It moves the content
of a BRAM in a circular motion on the screen. On the 8 on-board LEDs the
current state of the 8-bit frame counter is shown.
\subsection{Hardware Setup}
FIJI uses the FTDI chip on the breakout board to communicate with the
fault injection logic.
The VGA extension board shall be connected to
the 40 pin extension header as shown in Figure~\ref{fig:hx8k_connections}.
The pin connections are also documented in the physical constraint files
for the initial and the instrumented implementations.
\caption{HX8K Connections}
\subsection{Software Setup}
The Yosys Demo requires a Linux system with the \texttt{yosys}, \texttt{arachne-pnr},
and the IceStorm binaries (\texttt{icepack}, \ldots) in the system's execution path.
The entire instrumentation process is directed by GNU make.
As Yosys does not support VHDL as an input language, Synplify is
required to synthesize the FIJI logic and the wrapper. The original synthesis
step, the entire netlist instrumentation process, as well as the final
synthesis step combining the wrapper and the instrumented netlist, is handled
by Yosys.
Furthermore, a \texttt{FIJI\_ROOT} environment variable shall point to the
root directory where FIJI was cloned from the git repository.
\subsection{Executing the Demo Flow}
The entire instrumentation process is executed by two Makefiles (to be
executed in that order):
\item The initial synthesis step as well as the FIJI Setup and the
FIJI Instrument tool are executed by the Makfile found in
\texttt{docs/demos/tinyvga/impl/original/}. Run
$ make fiji-instrument
to synthesize the RTL design to a Verilog netlist, call FIJI Setup,
and finally instrument the netlist as required. A FIJI configuration
for some faults has already been provided. If necessary, select the
correct nets/drivers (other Yosys versions might generate a differing
netlist). The optional target \texttt{prog} generates a bitstream for the original design and
downloads it to a connected HX8K breakout board.
\item The second synthesis step, as well as run-time fault injection is
executed by the Makefile found in the directory \texttt{docs/demos/tinyvga/impl/instrumented/}.
To download the instrumented design to a connected board and launch FIJI EE
subsequently, execute
$ make prog && make fiji-launch
in this directory. This Makefile automatically synthesizes
the VHDL parts to a netlist using Synplify (the command and
options are defined in this file), combines the FIJI logic and
the instrumented netlist using Yosys, and finally generates
a bitstream for the HX8K device using the IceStorm tools.
\subsection{Run-Time Fault Injection}
The provided FIJI configuration instruments the MSBs of the three
VGA color signals, as well as the row and column addresses for the
image source on-chip RAM.
Once the design is downloaded and the FIJI EE GUI is launched, the following
things may be done:
\item Configure the correct serial device to communicate with the
FIJI hardware. A udev rule that symlinks the HX8K board to
\texttt{/dev/ttyHX8K} may be useful.
\item Check the connectivity by pressing the \emph{Update} button.
If no error message is shown in the logging box, the design
is ready for fault injection.
\item Perform sequence, manual, or random fault injections.
Faults are immediately visible by distorted VGA output. Since
the provided FIJI configuration does not alter the VGA timing,
this should work with all monitors.
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