Commit bdd8b684 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
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Added UART description

parent 0a10e791
......@@ -66,6 +66,24 @@ selection. If, however, area or timing is critical, fault injection units
can be configured to implement only one fault model each.
Fault injection units are daisy-chained in \texttt{\texttt{fault\_injection\_top}} as described in Section~\ref{sec:hw_fi_top}.
The UART unit consists of a receiver and a transmitter module. The receiver module
detects incoming symbols on the asynchronous serial interface, and forwards
them to the \ac{FIC} in a synchronous fashion. The interface from the UART receiver
to the \ac{FIC} consists of the data line, a data-valid signal,
and an additional line signalling the start of a byte. Framing errors on the asynchronous
interface (e.g., wrong stop bit polarity) are reported to the \ac{FIC}
using an error signal.
The transmitter module accepts messages on a parallel interface consisting
of the data bus and a data-valid signal. It signals when it is ready to do
so using an additional ready signal. The transmitter prepends a start bit, and
then shifts out the data bits followed by the parity bit and the stop bit.
The baud rate used by the receiver and transmitter can be statically configured
using the constant \texttt{c\_baudrate} defined in the \texttt{public\_config\_pkg}
VHDL package. It also depends on the clock frequency defined via \texttt{c\_frequency}
in the same package.
\fixme{Add this as footnote to the specification of \texttt{t\_fiu\_records}?
Due to the encoding of the forwarding/fault type in 3 bits, another 2 fault types can be added easily.
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