Commit bd474692 authored by Stefan Tauner's avatar Stefan Tauner
Browse files

instrument: make wrapper generator aware of top-level port name changes

parent d61b8233
...@@ -567,6 +567,10 @@ sub instrument_net { ...@@ -567,6 +567,10 @@ sub instrument_net {
if (defined($net->msb)) { if (defined($net->msb)) {
$driver_is_vector = 1; $driver_is_vector = 1;
} }
# If we are changing the name of a port of the top module we need to inform the VHDL generator
if ($mod->is_top) {
$connection->userdata(FIJI::VHDL->FIJI_USERDATA_PREV_PORTNAME, $connection->name);
}
# Change type of existing non-instrumented input to wire - # Change type of existing non-instrumented input to wire -
# practically transforming it to an ordinary wire that can easily be intrumented. # practically transforming it to an ordinary wire that can easily be intrumented.
$logger->debug("Transforming previous port named \"". $connection->name . "\" into an ordinary wire"); $logger->debug("Transforming previous port named \"". $connection->name . "\" into an ordinary wire");
...@@ -655,7 +659,7 @@ sub instrument_net { ...@@ -655,7 +659,7 @@ sub instrument_net {
# For ports we don't need to do that ourselves because Verilog::Perl will # For ports we don't need to do that ourselves because Verilog::Perl will
# generate a new apropriate net when linking the port. # generate a new apropriate net when linking the port.
if ($driver_is_port) { if ($driver_is_port) {
$logger->debug("Intermediate " . ($driver_is_port ? 'port' : 'wire') . " named \"" . $net_name_tmp . (defined($net->msb) ? "[" . $net->msb .":". $net->lsb . "]" : "") . "\" to patch \"$net_name\" will be generated automatically later"); $logger->debug("Intermediate port named \"" . $net_name_tmp . (defined($net->msb) ? "[" . $net->msb .":". $net->lsb . "]" : "") . "\" to patch \"$net_name\" will be generated automatically later");
} else { } else {
# If the driver is a vector then we will generate a vectored intermediate net as well. # If the driver is a vector then we will generate a vectored intermediate net as well.
# However, if the driver is a single-bit net or a single bit of a vector we generate # However, if the driver is a single-bit net or a single bit of a vector we generate
......
...@@ -39,9 +39,10 @@ use FIJI::Settings; ...@@ -39,9 +39,10 @@ use FIJI::Settings;
# FIJI_USERDATA_xxx is intended as key for the port->userdata{} hash # FIJI_USERDATA_xxx is intended as key for the port->userdata{} hash
# FIJI_USERDATA_PORTTYPE: type of the port (see FIJI_PORTTYPE_xxx enum) # FIJI_USERDATA_PORTTYPE: type of the port (see FIJI_PORTTYPE_xxx enum)
# FIJI_USERDATA_PREV_PORTNAME: original name of the port in case it was driving an instrumented net
# FIJI_USERDATA_FIU_INDEX: FIU# this FIJI_PORTTYPE_MODIFIED or FIJI_PORTTYPE_ORIGINAL should be connected to # FIJI_USERDATA_FIU_INDEX: FIU# this FIJI_PORTTYPE_MODIFIED or FIJI_PORTTYPE_ORIGINAL should be connected to
# FIJI_USERDATA_FD_INDEX: Fault Detection channel this FIJI_PORTTYPE_FAULT_DETECTION should be connected to # FIJI_USERDATA_FD_INDEX: Fault Detection channel this FIJI_PORTTYPE_FAULT_DETECTION should be connected to
use enum qw(FIJI_USERDATA_PORTTYPE FIJI_USERDATA_FIU_INDEX FIJI_USERDATA_FD_INDEX); use enum qw(FIJI_USERDATA_PORTTYPE FIJI_USERDATA_PREV_PORTNAME FIJI_USERDATA_FIU_INDEX FIJI_USERDATA_FD_INDEX);
# FIJI_PORTTYPE_xxx is intended to be used as value for port->userdata{FIJI::VHDL->FIJI_USERDATA_PORTTYPE} to determine the special port usage # FIJI_PORTTYPE_xxx is intended to be used as value for port->userdata{FIJI::VHDL->FIJI_USERDATA_PORTTYPE} to determine the special port usage
# FIJI_PORTTYPE_CLOCK: clock output to FIJI from DUT # FIJI_PORTTYPE_CLOCK: clock output to FIJI from DUT
...@@ -374,9 +375,10 @@ sub generate_wrapper_module { ...@@ -374,9 +375,10 @@ sub generate_wrapper_module {
} }
} else { } else {
my $extportname = (defined($port->userdata(FIJI_USERDATA_PREV_PORTNAME))) ? $port->userdata(FIJI_USERDATA_PREV_PORTNAME) : $port->name;
# add to externally connected DUT ports # add to externally connected DUT ports
push @ext_ports, (($port->name) . " : " . ($port->direction) . " " . (port2vhdtype($port))); push @ext_ports, ("$extportname : " . ($port->direction) . " " . (port2vhdtype($port)));
push @dut_port_maps, (($port->name) . " => " . ($port->name)); push @dut_port_maps, ($port->name . " => $extportname");
} }
} }
......
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