Commit b72e6ff1 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Removed project files and tst files from TMR VGA demo

parent 57bf8504
; FIJI::ConfigSorted 0.1
; Thu Aug 18 12:25:31 2016
[CONSTS]
COMPLETION_SCRIPT=
FIJI_CFG=fiji.cfg
HALT_ON_CRC_ERROR=1
HALT_ON_FAULT_DETECT=1
HALT_ON_ID_ERROR=1
HALT_ON_UART_ERROR=1
HALT_ON_UNDERRUN=0
INITIAL_RESET=0
INITIAL_TRIGGER=NONE
MAX_DURATION_T1=10000000
MAX_DURATION_T2=10000000
MIN_DURATION_T1=1000000
MIN_DURATION_T2=1000000
MULTIFAULT=1
NUM_TESTS=1
PROB_DELAY=0.1
PROB_SEU=0.1
PROB_STUCK_AT_0=0.1
PROB_STUCK_AT_1=0.1
PROB_STUCK_OPEN=0.1
REPEAT=0
REPEAT_OFFSET=0
UART=/dev/ttyUSB0
[TEST0]
FIU_0_FAULT_1=NONE
FIU_0_FAULT_2=NONE
FIU_1_FAULT_1=NONE
FIU_1_FAULT_2=NONE
FIU_2_FAULT_1=NONE
FIU_2_FAULT_2=NONE
RESET_DUT_AFTER_CONFIG=0
TIMER_VALUE_1=1000000
TIMER_VALUE_2=1000000
TRIGGER=NONE
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.0 Build 156 04/24/2013 SJ Full Version
# Date created = 12:32:31 August 18, 2016
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "13.0"
DATE = "12:32:31 August 18, 2016"
# Revisions
PROJECT_REVISION = "fiji_top"
set_location_assignment PIN_K22 -to s_blue_o[0]
set_location_assignment PIN_K21 -to s_blue_o[1]
set_location_assignment PIN_J22 -to s_blue_o[2]
set_location_assignment PIN_K18 -to s_blue_o[3]
set_location_assignment PIN_H22 -to s_green_o[0]
set_location_assignment PIN_J17 -to s_green_o[1]
set_location_assignment PIN_K17 -to s_green_o[2]
set_location_assignment PIN_J21 -to s_green_o[3]
set_location_assignment PIN_L21 -to s_hsync_o
set_location_assignment PIN_H19 -to s_red_o[0]
set_location_assignment PIN_H17 -to s_red_o[1]
set_location_assignment PIN_H20 -to s_red_o[2]
set_location_assignment PIN_H21 -to s_red_o[3]
set_location_assignment PIN_J6 -to s_tmr_en_i
set_location_assignment PIN_J1 -to s_ledg_o[0]
set_location_assignment PIN_J2 -to s_ledg_o[1]
set_location_assignment PIN_J3 -to s_ledg_o[2]
set_location_assignment PIN_H1 -to s_ledg_o[3]
set_location_assignment PIN_H2 -to s_reset_x_i
set_location_assignment PIN_L22 -to s_vsync_o
set_location_assignment PIN_G21 -to s_clk_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_blue_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_blue_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_blue_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_blue_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_clk_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_green_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_green_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_green_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_green_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_hsync_o
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_ledg_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_ledg_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_ledg_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_ledg_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_red_o[0]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_red_o[1]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_red_o[2]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_red_o[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_reset_x_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_tmr_en_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_vsync_o
set_instance_assignment -name SLEW_RATE 2 -to s_blue_o[3]
set_instance_assignment -name SLEW_RATE 2 -to s_blue_o[2]
set_instance_assignment -name SLEW_RATE 2 -to s_blue_o[1]
set_instance_assignment -name SLEW_RATE 2 -to s_blue_o[0]
set_instance_assignment -name SLEW_RATE 2 -to s_green_o[3]
set_instance_assignment -name SLEW_RATE 2 -to s_green_o[2]
set_instance_assignment -name SLEW_RATE 2 -to s_green_o[1]
set_instance_assignment -name SLEW_RATE 2 -to s_green_o[0]
set_instance_assignment -name SLEW_RATE 2 -to s_hsync_o
set_instance_assignment -name SLEW_RATE 2 -to s_ledg_o[3]
set_instance_assignment -name SLEW_RATE 2 -to s_ledg_o[2]
set_instance_assignment -name SLEW_RATE 2 -to s_ledg_o[1]
set_instance_assignment -name SLEW_RATE 2 -to s_ledg_o[0]
set_instance_assignment -name SLEW_RATE 2 -to s_red_o[3]
set_instance_assignment -name SLEW_RATE 2 -to s_red_o[2]
set_instance_assignment -name SLEW_RATE 2 -to s_red_o[1]
set_instance_assignment -name SLEW_RATE 2 -to s_red_o[0]
set_instance_assignment -name SLEW_RATE 2 -to s_vsync_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_blue_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_blue_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_blue_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_blue_o[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_green_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_green_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_green_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_green_o[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_hsync_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_ledg_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_ledg_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_ledg_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_ledg_o[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_red_o[3]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_red_o[2]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_red_o[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_red_o[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_vsync_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_clk_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_reset_x_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_tmr_en_i
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_location_assignment PIN_G3 -to s_fiji_trigger_ext_i
set_location_assignment PIN_V6 -to s_fiji_tx_o
set_location_assignment PIN_V7 -to s_fiji_rx_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_fiji_rx_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_fiji_trigger_ext_i
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to s_fiji_tx_o
set_instance_assignment -name SLEW_RATE 2 -to s_fiji_tx_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_fiji_tx_o
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_fiji_rx_i
set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to s_fiji_trigger_ext_i
\ No newline at end of file
#-- Synopsys, Inc.
#-- Version I-2013.09-SP1
#-- Project file /home/fibich/git/vecs/fiji/fiji_public/docs/demos/tmr_vga/fiji/de0_test_1/synp/spriteflyer_top.prj
#project files
add_file -vhdl -lib work "../fiji/tmr_vga_demo_wrapper.vhd"
add_file -vhdl -lib work "../fiji/tmr_vga_demo_config_pkg.vhd"
add_file -verilog "../fiji/tmr_vga_demo_instrumented.vqm"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_struc.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_selection_type_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/private_config_pkg.vhd"
add_file -fpga_constraint "./spriteflyer_top.fdc"
#implementation: "de0"
impl -add de0 -type fpga
#
#implementation attributes
set_option -vlog_std sysv
set_option -project_relative_includes 1
#device options
set_option -technology CYCLONEIII
set_option -part EP3C16
set_option -package FC484
set_option -speed_grade -6
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "work.fiji_top"
# altera_options
set_option -RWCheckOnRam 1
# mapper_options
set_option -frequency auto
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# Altera STRATIX
set_option -run_prop_extract 1
set_option -maxfan 30
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
set_option -quartus_version 13.0
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./de0/spriteflyer_top.vqm"
impl -active "de0"
; FIJI::ConfigSorted 0.1
; Thu Aug 18 10:17:57 2016
[CONSTS]
COMPLETION_SCRIPT=
FIJI_CFG=fiji.cfg
HALT_ON_CRC_ERROR=1
HALT_ON_FAULT_DETECT=1
HALT_ON_ID_ERROR=1
HALT_ON_UART_ERROR=1
HALT_ON_UNDERRUN=0
INITIAL_RESET=0
INITIAL_TRIGGER=NONE
MAX_DURATION_T1=10000000
MAX_DURATION_T2=10000000
MIN_DURATION_T1=1000000
MIN_DURATION_T2=1000000
MULTIFAULT=1
NUM_TESTS=1
PROB_DELAY=0.1
PROB_SEU=0.1
PROB_STUCK_AT_0=0.1
PROB_STUCK_AT_1=0.1
PROB_STUCK_OPEN=0.1
REPEAT=0
REPEAT_OFFSET=0
UART=/dev/ttyUSB0
[TEST0]
FIU_0_FAULT_1=NONE
FIU_0_FAULT_2=NONE
FIU_1_FAULT_1=NONE
FIU_1_FAULT_2=NONE
FIU_2_FAULT_1=NONE
FIU_2_FAULT_2=NONE
RESET_DUT_AFTER_CONFIG=0
TIMER_VALUE_1=1000000
TIMER_VALUE_2=1000000
TRIGGER=NONE
#-- Synopsys, Inc.
#-- Version I-2013.09-SP1
#-- Project file /home/fibich/git/vecs/fiji-internal/docs/demos/tmr_vga/fiji/zybo_test_1/synp/spriteflyer_top.prj
#project files
add_file -vhdl -lib work "../fiji/spriteflyer_top_wrapper.vhd"
add_file -vhdl -lib work "../fiji/spriteflyer_top_config_pkg.vhd"
add_file -fpga_constraint "../fiji/spriteflyer_top_constraints.synplify.fdc"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_controller_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_top_struc.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_tx_buffer_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_uart_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_injection_unit_rtl.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/fault_selection_type_pkg.vhd"
add_file -vhdl -lib work "../../../../../../hw/rtl/private_config_pkg.vhd"
add_file -fpga_constraint "./zybo/spriteflyer_top.fdc"
add_file -verilog "../fiji/spriteflyer_top_instrumented.vm"
#implementation: "zybo"
impl -add zybo -type fpga
#
#implementation attributes
set_option -vlog_std sysv
set_option -project_relative_includes 1
#device options
set_option -technology Zynq
set_option -part XC7Z010
set_option -package CLG400
set_option -speed_grade -1
set_option -part_companion ""
#compilation/mapping options
set_option -use_fsm_explorer 0
# mapper_options
set_option -frequency auto
set_option -write_verilog 1
set_option -write_vhdl 0
set_option -srs_instrumentation 1
# xilinx_options
set_option -RWCheckOnRam 1
# Xilinx Virtex2
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fix_gated_and_generated_clocks 1
# Xilinx Zynq
set_option -use_vivado 1
set_option -enable_prepacking 1
# sequential_optimization_options
set_option -symbolic_fsm_compiler 1
# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1
set_option -multi_file_compilation_unit 1
# Compiler Options
set_option -auto_infer_blackbox 0
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
#set result format/file last
project -result_file "./zybo/spriteflyer_top.vm"
impl -active "zybo"
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