Netlist: some cleanups in get_connection_object() and elsewhere

bin/FIJI/Netlist.pm

@@ -493,7 +493,7 @@ sub instrument_net {
     if (defined $msb && defined $lsb) {
         if ($msb ne $lsb) {
             # We dont support the instrumentation of vectors (only sinlge indices of busses).
-            return "The given net to instrument is a vector with multiple bits.\nThis is not supported.\nMay you want to instrument a single bit of said vector instead?";
+            return "The given net to instrument is a vector with multiple bits.\nThis is not supported.\nMaybe you want to instrument a single bit of said vector instead?";
             # $idx         = "[".$msb.":".$lsb."]";
             # $idx_postfix = "_".$msb."_".$lsb."_";
         } else {
@@ -864,15 +864,15 @@ sub get_connection_object {
         }
     } elsif ($connection_type eq "ASSIGN") {
         if ($connection_path =~ /^(.+)\Q$SEP\E(.+)$/) {
-            my $lhs = $2;
+            my $net = $2;
 
-            $logger->trace("Looking for assignment to/from \"$2\" in module \"$1\"...");
+            $logger->trace("Looking for assignment to/from \"$net\" in module \"$1\"...");
             my $mod = $self->{'nl'}->find_module($1);
 
             if (defined $mod) {
                 my $assign;
                 for my $a (grep { $_->isa("Verilog::Netlist::ContAssign") } $mod->statements) {
-                    if ($a->lhs eq $lhs || $a->rhs =~ /\Q$lhs\E/) {
+                    if ($a->lhs =~ /\Q$net\E/ || $a->rhs =~ /\Q$net\E/) {
                         $assign = $a;
                         $logger->trace(sprintf("Constant assignment: \"%s\" = \"%s\"", $a->lhs, $a->rhs));
                         last;
@@ -911,7 +911,7 @@ sub _get_net_connections_from_path {
 # @brief breaks up a verilog concatenation into single net elements
 #
 # @param concat     string (including the {}) forming a verilog concatenation
-# @return arrayref   array reference containing the individual concatenated verilog expressions in the given string
+# @return arrayref  array reference containing the individual concatenated verilog expressions in the given string
 sub _untie_concatenations {
     my $logger = get_logger("");
     my ($self, $concat) = @_;
@@ -933,9 +933,9 @@ sub _untie_concatenations {
 #
 # @param net                    the net to be examined
 # @param connection_hashref     a hashref where the results can be placed
-#                               connection_hashref->{'drivers'} contains a list of driver cells
-#                               connection_hashref->{'driven'} contains a list of driven cells
-#                               connection_hashref->{'connected'} contains a list cells connected to the
+#                               connection_hashref->{'drivers'} contains a list of things driving the net
+#                               connection_hashref->{'driven'} contains a list of things driven by this net
+#                               connection_hashref->{'connected'} contains a list things connected to the
 #                               net but driver/driven cannot be decided
 # @param bit                    one bit of the net to check for connections (optional, only useful for vectored nets)
 # @param driver_path            the path to the driver of this net (optional but depends on driver_type)
@@ -994,7 +994,7 @@ sub _get_net_connections {
 
     $logger->debug("Net \"" . $mod->name . HIERSEP . $net_name . "\", connections:");
 
-    # find nets driven by continuous assignment (e.g., constant or inverter)
+    # find drivers and driven nets in continuous assignments
     foreach my $statement ($mod->statements) {
         # FIXME: handle concatenations
         # my $rhs_nets_names = $self->_untie_concatenations($statement->rhs);
@@ -1031,7 +1031,7 @@ sub _get_net_connections {
         }
     }
 
-    # find nets driven by this module's input ports
+    # find nets driven by this module's input ports or driving its outputs
     foreach my $port ($mod->ports) {
         if (defined $port->net && ($port->net->name eq $net_name)) {
             $logger->debug("    port:   \"" . $mod->name . HIERSEP . $port->name . "\"");
@@ -1067,11 +1067,6 @@ sub _get_net_connections {
         foreach my $pin ($cell->pins) {
             foreach my $netname (@{$pin->netnames}) {
                 if ($netname->{'netname'} eq $net_name) {
-                    if (!_is_pinrange_in_net($net->msb, $net->lsb, $net)) {
-                        $logger->warn("Out of range (of net \"$net_name\")\n");
-                        next;
-                    }
-
                     my $dir = (!defined($pin->port)) ? "unknown" : ($pin->port->direction eq 'in') ? "in" : "out";
                     $logger->debug("    pin (" . $dir . ") \"" . $pin->cell->name . HIERSEP . $pin->name . "\"");
                     # The pin might be the driver but we can't be sure without a preselection.