Commit a6c64805 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Added benchmark Verilog code + current status dump

parent 4baa0a08
/*
* Benchmark Verilog "Netlist" File
* If Verilog-Perl interconnects this correctly, we're happy...
*
* $LastChangedBy$
* $LastChangedDate$
*/
/*
* This is the Cell definition.
* It would be located in the FPGA primitive library, which we don't want to
* load, thus Verilog::Perl has no knowledge about the port widths
*
* module mod (a,y);
* input [3:0] a;
* output y;
* wire [3:0] b;
* wire c;
*
* // Some Functionality
*
* endmodule
*
*/
module top(i,o);
input [31:0] i;
output [31:0] o;
wire [3:0] somebus, someotherbus;
wire somenet_1,somenet_2;
wire [29:0] somewidebus;
assign somewidebus=i[31:2];
assign o[1]=somenet_1;
assign o[2]=somenet_2;
assign o[0]=1'b0;
assign o[3]=someotherbus[2];
assign o[28:4]=25'b0;
assign o[31]=~somenet_1;
mod instmod_1 (
.a(somebus),
.y(somenet_1)
);
mod instmod_2 (
.a(somebus),
.y(someotherbus[2])
);
mod instmod_3 (
.a(somewidebus[24:21]),
.y(somenet_2)
);
mod instmod_4 (
.a(i[31:27]),
.y(o[29])
);
mod instmod_5 (
.a({somenet_1,someotherbus[2],somewidebus[2:1]}),
.y(o[30])
);
/*
FIXME Not allowed in Verilog Language??
mod instmod_6 (
.a[0](somenet_1),
.a[1](someotherbus[2]),
.a[3:2](somewidebus[2:1])
.y(o[31]);
);
*/
endmodule
2015-08-05 15:50:30.311 INFO - Successfully read in netlist from file "test/benchmark.v". (FIJI/Netlist.pm:110> FIJI::Netlist::read_file)
$VAR1 = bless( {
'nl' => bless( {
'_libraries_done' => {},
'_interfaces' => {},
'link_read_nonfatal' => 1,
'remove_defines_without_tick' => 0,
'logger' => bless( {
'_errors' => 0,
'_error_unlink_files' => {},
'_warnings' => 0
}, 'Verilog::Netlist::Logger' ),
'preproc' => 'Verilog::Preproc',
'_need_link' => [],
'symbol_table' => [
1,
undef,
{
'top' => [
15,
$VAR1->{'nl'}{'symbol_table'},
{}
]
}
],
'link_read' => 1,
'_files' => {
'test/benchmark.v' => bless( [
'test/benchmark.v',
'benchmark',
$VAR1->{'nl'},
{},
{},
undef,
0,
bless( {
'keep_whitespace' => 1,
'options' => bless( {
'module_dir' => [
'.'
],
'libext' => [
'.v'
],
'unparsed' => [],
'vcs_style' => 1,
'depend_files' => {
'test/benchmark.v' => 1
},
'filename_expansion' => 0,
'define_warnings' => 1,
'fileline' => ':0',
'_file_path_cache' => {
'test/benchmark.v' => 'test/benchmark.v'
},
'incdir' => [
'.'
],
'library' => [],
'defines' => {
'SV_COV_ERROR' => [
-1,
undef,
1
],
'SV_COV_FSM_STATE' => [
21,
undef,
1
],
'SV_COV_STOP' => [
1,
undef,
1
],
'SV_COV_PARTIAL' => [
2,
undef,
1
],
'SV_COV_OK' => [
1,
undef,
1
],
'SV_COV_HIER' => [
11,
undef,
1
],
'SV_COV_CHECK' => [
3,
undef,
1
],
'SV_COV_ASSERTION' => [
20,
undef,
1
],
'SV_COV_MODULE' => [
10,
undef,
1
],
'SV_COV_STATEMENT' => [
22,
undef,
1
],
'SV_COV_RESET' => [
2,
undef,
1
],
'SV_COV_NOCOV' => [
0,
undef,
1
],
'SV_COV_START' => [
0,
undef,
1
],
'SV_COV_OVERFLOW' => [
-2,
undef,
1
],
'SV_COV_TOGGLE' => [
23,
undef,
1
]
},
'gcc_style' => 1
}, 'Verilog::Getopt' ),
'parent' => $VAR1->{'nl'}{'_files'}{'test/benchmark.v'},
'keep_comments' => 0,
'ieee_predefined' => 1,
'_cthis' => 23613856,
'line_directives' => 1,
'pedantic' => 0,
'synthesis' => 0
}, 'Verilog::Preproc' ),
{},
{
'top' => bless( [
'top',
'test/benchmark.v',
26,
$VAR1->{'nl'},
'module',
{},
{},
[],
undef,
{
'i' => bless( [
'i',
'test/benchmark.v',
27,
{},
{},
'in',
'[31:0]',
undef,
'',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
bless( [
'i',
'test/benchmark.v',
27,
{},
{},
'[31:0]',
'port',
'',
undef,
'',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
'',
'',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[9]{'i'},
'31',
'0',
undef,
undef,
1,
undef,
1,
undef,
undef
], 'Verilog::Netlist::Net' ),
undef
], 'Verilog::Netlist::Port' ),
'o' => bless( [
'o',
'test/benchmark.v',
28,
{},
{},
'out',
'[31:0]',
undef,
'',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
bless( [
'o',
'test/benchmark.v',
28,
{},
{},
'[31:0]',
'port',
'',
undef,
'',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
'',
'',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[9]{'o'},
'31',
'0',
undef,
1,
undef,
undef,
1,
undef,
undef
], 'Verilog::Netlist::Net' ),
undef
], 'Verilog::Netlist::Port' )
},
[
'i',
'o'
],
{
'somewidebus' => bless( [
'somewidebus',
'test/benchmark.v',
32,
{},
{},
'[29:0]',
'net',
'wire',
undef,
'',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
'',
'',
undef,
'29',
'0',
undef,
undef,
undef,
undef,
1,
undef,
undef
], 'Verilog::Netlist::Net' ),
'someotherbus' => bless( [
'someotherbus',
'test/benchmark.v',
30,
{},
{},
'[3:0]',
'net',
'wire',
undef,
'',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
'',
'',
undef,
'3',
'0',
undef,
undef,
undef,
undef,
1,
undef,
undef
], 'Verilog::Netlist::Net' ),
'i' => $VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[9]{'i'}[10],
'somenet_1' => bless( [
'somenet_1',
'test/benchmark.v',
31,
{},
{},
'',
'net',
'wire',
undef,
'',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
'',
'',
undef,
undef,
undef,
undef,
undef,
undef,
undef,
1,
undef,
undef
], 'Verilog::Netlist::Net' ),
'o' => $VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[9]{'o'}[10],
'somebus' => bless( [
'somebus',
'test/benchmark.v',
30,
{},
{},
'[3:0]',
'net',
'wire',
undef,
'',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
'',
'',
undef,
'3',
'0',
undef,
undef,
undef,
undef,
1,
undef,
undef
], 'Verilog::Netlist::Net' ),
'somenet_2' => bless( [
'somenet_2',
'test/benchmark.v',
31,
{},
{},
'',
'net',
'wire',
undef,
'',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
'',
'',
undef,
undef,
undef,
undef,
undef,
undef,
undef,
1,
undef,
undef
], 'Verilog::Netlist::Net' )
},
{
'instmod_1' => bless( [
'instmod_1',
'test/benchmark.v',
42,
{},
{},
undef,
'mod',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
'',
{
'y' => bless( [
'y',
'test/benchmark.v',
44,
{},
{},
undef,
'somenet_1',
'y',
'2',
1,
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[12]{'instmod_1'},
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[11]{'somenet_1'},
undef,
undef
], 'Verilog::Netlist::Pin' ),
'a' => bless( [
'a',
'test/benchmark.v',
43,
{},
{},
undef,
'somebus',
'a',
'1',
1,
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[12]{'instmod_1'},
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[11]{'somebus'},
undef,
undef
], 'Verilog::Netlist::Pin' )
},
undef,
undef,
undef,
undef
], 'Verilog::Netlist::Cell' ),
'instmod_3' => bless( [
'instmod_3',
'test/benchmark.v',
52,
{},
{},
undef,
'mod',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
'',
{
'a' => bless( [
'a',
'test/benchmark.v',
53,
{},
{},
undef,
'somewidebus[24:21]',
'a',
'1',
1,
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[12]{'instmod_3'},
undef,
undef,
undef
], 'Verilog::Netlist::Pin' ),
'y' => bless( [
'y',
'test/benchmark.v',
54,
{},
{},
undef,
'somenet_2',
'y',
'2',
1,
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[12]{'instmod_3'},
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[11]{'somenet_2'},
undef,
undef
], 'Verilog::Netlist::Pin' )
},
undef,
undef,
undef,
undef
], 'Verilog::Netlist::Cell' ),
'instmod_4' => bless( [
'instmod_4',
'test/benchmark.v',
57,
{},
{},
undef,
'mod',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
'',
{
'y' => bless( [
'y',
'test/benchmark.v',
59,
{},
{},
undef,
'o[29]',
'y',
'2',
1,
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[12]{'instmod_4'},
undef,
undef,
undef
], 'Verilog::Netlist::Pin' ),
'a' => bless( [
'a',
'test/benchmark.v',
58,
{},
{},
undef,
'i[31:27]',
'a',
'1',
1,
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[12]{'instmod_4'},
undef,
undef,
undef
], 'Verilog::Netlist::Pin' )
},
undef,
undef,
undef,
undef
], 'Verilog::Netlist::Cell' ),
'instmod_5' => bless( [
'instmod_5',
'test/benchmark.v',
62,
{},
{},
undef,
'mod',
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'},
'',
{
'y' => bless( [
'y',
'test/benchmark.v',
64,
{},
{},
undef,
'o[30]',
'y',
'2',
1,
$VAR1->{'nl'}{'_files'}{'test/benchmark.v'}[9]{'top'}[12]{'instmod_5'},