Commit 96f6d3ee authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Added register for latching fault detection bits

parent f8c3c981
......@@ -59,12 +59,23 @@ architecture struc of fault_injection_top is
begin -- architecture struc
-- do something with the fault detection data
s_fault_detect <= s_fiji_fault_detect_i(1 downto 0) xor c_fault_detect_invert_mask;
-- multiplex reset
s_reset_n <= '0' when s_fiji_reset_ext_i = c_reset_ext_active or
s_fiji_reset_dut_out_i = c_reset_dut_out_active else '1';
s_reset_n <= '0' when (s_fiji_reset_ext_i = c_reset_ext_active or
s_fiji_reset_dut_out_i = c_reset_dut_out_active) else '1';
-- purpose: latching the fault detection signals once they become active
-- type : sequential
-- inputs : s_fiji_clk_i, s_reset_n,s_fiji_fault_detect_i,s_fault_detect
-- outputs: s_fault_detect
p_fault_detect_ff : process (s_fiji_clk_i,s_reset_n)
begin
if s_reset_n = '0' then
s_fault_detect <= (others => '0');
elsif s_fiji_clk_i'event and s_fiji_clk_i = '1' then
s_fault_detect <= s_fault_detect or (s_fiji_fault_detect_i(1 downto 0) xor c_fault_detect_invert_mask);
end if;
end process;
-- instantiate FIUs according to config
-- connect FIUs' shift registers from low to high
......
......@@ -49,7 +49,7 @@ vcom -lint -check_synthesis +cover=sbce ../rtl/fault_injection_controller_.vhd
vcom -lint -check_synthesis +cover=sbce ../rtl/fault_injection_controller_rtl.vhd -pslfile psl/fault_injection_controller.psl
vcom -lint -check_synthesis +cover=sbce ../rtl/fault_injection_top_.vhd
vcom -lint -check_synthesis +cover=sbce ../rtl/fault_injection_top_struc.vhd
vcom -lint -check_synthesis +cover=sbce ../rtl/fault_injection_top_struc.vhd -pslfile psl/fault_injection_top.psl
vcom -2008 ../tb/fault_injection_top_tb.vhd
......
......@@ -9,7 +9,7 @@ add wave -noupdate /fault_injection_top_tb/DUT/s_fiji_rx_i
add wave -noupdate /fault_injection_top_tb/DUT/s_fiji_trigger_ext_i
add wave -noupdate /fault_injection_top_tb/DUT/s_fiji_trigger_dut_i
add wave -noupdate /fault_injection_top_tb/DUT/s_fiji_original_i
add wave -noupdate /fault_injection_top_tb/s_fiji_fault_detect_i
add wave -noupdate -expand /fault_injection_top_tb/s_fiji_fault_detect_i
add wave -noupdate -divider Outputs
add wave -noupdate /fault_injection_top_tb/DUT/s_fiji_tx_o
add wave -noupdate /fault_injection_top_tb/DUT/s_fiji_reset_dut_in_o
......@@ -36,6 +36,7 @@ add wave -noupdate /fault_injection_top_tb/DUT/s_buffer_full
add wave -noupdate /fault_injection_top_tb/DUT/s_buffer_empty
add wave -noupdate /fault_injection_top_tb/DUT/s_buffer_rdrq
add wave -noupdate /fault_injection_top_tb/DUT/s_tx_state
add wave -noupdate /fault_injection_top_tb/DUT/s_fault_detect
add wave -noupdate -divider FIUs
add wave -noupdate /fault_injection_top_tb/DUT/s_update_fius
add wave -noupdate -divider {Fault Select}
......@@ -72,8 +73,10 @@ add wave -noupdate /fault_injection_top_tb/DUT/s_buffer_empty
add wave -noupdate /fault_injection_top_tb/DUT/s_buffer_rdrq
add wave -noupdate /fault_injection_top_tb/DUT/generate_FIUs(7)/generate_FIUs_greater_0/i_fault_injection_unit/g_lfsr_mask
add wave -noupdate /fault_injection_top_tb/DUT/generate_FIUs(7)/generate_FIUs_greater_0/i_fault_injection_unit/s_stuck_open
add wave -noupdate /fault_injection_top_tb/DUT/assert__p_fd
add wave -noupdate /fault_injection_top_tb/DUT/assert__p_fd2
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {9185660000 ps} 1} {{Cursor 3} {0 ps} 0}
WaveRestoreCursors {{Cursor 1} {9185660000 ps} 1} {{Cursor 3} {16078 ps} 0}
quietly wave cursor active 2
configure wave -namecolwidth 759
configure wave -valuecolwidth 344
......@@ -89,4 +92,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits us
update
WaveRestoreZoom {0 ps} {3150 us}
WaveRestoreZoom {2999908675 ps} {3000004807 ps}
......@@ -8,7 +8,7 @@
-- http://vecs.technikum-wien.at --
-- --
--------------------------------------------------------------------------------
-- File: fault_injection_unit.psl --
-- File: fault_injection_logic.psl --
-- $Author$ --
-- Created on: 21.04.2014 --
-- $Date$ --
......
--------------------------------------------------------------------------------
-- University of Applied Sciences Technikum Wien --
-- --
-- Department of Embedded Systems --
-- http://embsys.technikum-wien.at --
-- --
-- Josef Ressel Center for Verification of Embedded Computing Systems --
-- http://vecs.technikum-wien.at --
-- --
--------------------------------------------------------------------------------
-- File: fault_injection_top.psl --
-- $Author$ --
-- Created on: 27.05.2014 --
-- $Date$ --
-- --
-- Description: --
-- Assertions specifying the behavior of the FIC --
--------------------------------------------------------------------------------
library work;
use work.public_config_pkg.c_fault_detect_invert_mask;
use work.private_config_pkg.c_num_fault_detect_nets;
vunit fit (fault_injection_top(struc)) {
default clock is rising_edge(s_fiji_clk_i);
property p_fd is forall i in {0 to c_num_fault_detect_nets-1}:
s_fault_detect(i) = '0' until (s_fiji_fault_detect_i(i) /=
c_fault_detect_invert_mask(i));
property p_fd2 is forall i in {0 to c_num_fault_detect_nets-1}:
always (s_fault_detect(i) = '0' and s_fiji_fault_detect_i(i) /= c_fault_detect_invert_mask(i) and s_reset_n = '1') -> next
s_fault_detect(i) = '1';
property p_fd3 is forall i in {0 to c_num_fault_detect_nets-1}:
always (s_fault_detect(i) = '1') -> next s_fault_detect(i) = '1';
assert p_fd report "Invalid fault detect value.";
assert p_fd2 report "Invalid fault detect value.";
assert p_fd3 report "Invalid fault detect value.";
}
\ No newline at end of file
......@@ -145,6 +145,7 @@ begin -- architecture sim
while true loop
uniform(seed1, seed2, rand);
s_fiji_fault_detect_i <= std_logic_vector(to_unsigned(integer(round(rand*3.0)), 2));
wait for 1 us;
wait until s_fiji_clk_i = '1';
end loop;
end process p_fault_detect;
......
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