Commit 898e944e authored by Stefan Tauner's avatar Stefan Tauner
Browse files

netlist: remember previous driver instance and bit

This is needed to fix the first instrumentation of a vector when
instrumenting the second bit.
parent 33b9356d
...@@ -547,6 +547,7 @@ sub instrument_net { ...@@ -547,6 +547,7 @@ sub instrument_net {
my $driver_is_vector = 0; my $driver_is_vector = 0;
my $driver_is_port = 0; my $driver_is_port = 0;
my $driver_bit = $msb; my $driver_bit = $msb;
my $driver;
foreach my $connection (@{$connections{'drivers'}}) { foreach my $connection (@{$connections{'drivers'}}) {
if (ref($connection) eq "Verilog::Netlist::Pin") { if (ref($connection) eq "Verilog::Netlist::Pin") {
# If the driver is a pin of a (sub)cell, connect this pin to the intermediate net # If the driver is a pin of a (sub)cell, connect this pin to the intermediate net
...@@ -554,6 +555,7 @@ sub instrument_net { ...@@ -554,6 +555,7 @@ sub instrument_net {
# FIXME: do concatenations really work? They are apparently split already by Verilog::perl but... # FIXME: do concatenations really work? They are apparently split already by Verilog::perl but...
for my $netname ($connection->netnames) { for my $netname ($connection->netnames) {
if ($netname->{'netname'} eq $net->name) { if ($netname->{'netname'} eq $net->name) {
$driver = $connection;
$netname->{'netname'} = $net_name_tmp; # FIXME: do we need to force a re-link (by deleting $connection->nets)? $netname->{'netname'} = $net_name_tmp; # FIXME: do we need to force a re-link (by deleting $connection->nets)?
# This net is a vector if the underlying net is a bus and we do not just select a single bit # This net is a vector if the underlying net is a bus and we do not just select a single bit
# If driver is a vector we need a vectored intermediate bus. # If driver is a vector we need a vectored intermediate bus.
...@@ -577,6 +579,7 @@ sub instrument_net { ...@@ -577,6 +579,7 @@ sub instrument_net {
if (defined($net->msb)) { if (defined($net->msb)) {
$driver_is_vector = 1; $driver_is_vector = 1;
} }
$driver = $connection;
# If we are changing the name of a port of the top module we need to inform the VHDL generator # If we are changing the name of a port of the top module we need to inform the VHDL generator
if ($mod->is_top) { if ($mod->is_top) {
$connection->userdata(FIJI::VHDL->FIJI_USERDATA_PREV_PORTNAME, $connection->name); $connection->userdata(FIJI::VHDL->FIJI_USERDATA_PREV_PORTNAME, $connection->name);
...@@ -607,6 +610,7 @@ sub instrument_net { ...@@ -607,6 +610,7 @@ sub instrument_net {
$logger->fatal("Found port name in continuous assignment. This is not supported yet."); $logger->fatal("Found port name in continuous assignment. This is not supported yet.");
return "BORKED"; return "BORKED";
} }
$driver = $connection;
if (defined($connection->userdata->{'fiji_driver_bit'})) { if (defined($connection->userdata->{'fiji_driver_bit'})) {
$driver_is_vector = 1; $driver_is_vector = 1;
$driver_bit = $connection->userdata->{'fiji_driver_bit'}; $driver_bit = $connection->userdata->{'fiji_driver_bit'};
...@@ -669,7 +673,13 @@ sub instrument_net { ...@@ -669,7 +673,13 @@ sub instrument_net {
} else { } else {
$logger->debug("Generating intermediate wire named \"" . $net_name_tmp . "\" to patch \"$net_name\""); $logger->debug("Generating intermediate wire named \"" . $net_name_tmp . "\" to patch \"$net_name\"");
} }
$mod->new_net(@net_cfg); $net_tmp = $mod->new_net(@net_cfg);
# If we possibly instrument other bits we need to remember some things
if (defined($net->msb)) {
$net_tmp->userdata("first_instrumented_bit", $driver_bit);
$net_tmp->userdata("first_driver", $driver);
$logger->debug("Remembering the first instrumented bit ($driver_bit) assigned to \"" . $net_name_tmp . "\" driven by \"" . $driver->name . "\"");
}
} }
# 3+4.) Assign injected (and uninjected bits of vectors) to previous signal. # 3+4.) Assign injected (and uninjected bits of vectors) to previous signal.
......
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