Updated toolflow figure

docs/technical_reference_manual/content/04-hardware.tex

@@ -120,4 +120,4 @@ registers.
     \caption{Top-level VHDL Outputs}
     \input{content/tab_vhdl_outputs.tex}
     \label{tab:toplevel_outputs}
-\end{table}
\ No newline at end of file
+\end{table}

docs/tex_common/img/fiji_flow.tex

@@ -122,7 +122,9 @@
     \node [ourtool,  left of=inv,node distance=2cm] (dlgui)  {\texttt{fiji\_ee\_gui.pl}};
     \node [ourtool,  right of=inv,node distance=2cm] (dlcli) {\texttt{fiji\_ee.pl}};
     \node [userdoc, above left of=dlgui, node distance=3.5cm] (tstconf) {Test\\Configuration};
+    \node [document, left of=fpga, node distance=3.5cm] (templ) {RTL \& Gate-Level \\ Simulation \\ Templates};
     \node [below of=dlcli, node distance=10.1cm] (inv2) {};
+    \node [above of=templ] (inv3) {};
 
 
    % \path [rectangle,draw,dotted] ($(synthconst.north) + (-2,2)$) -| ($(orignetlist.south) + (2,-7)$) -| ($(synthconst.north) + (-2,2)$);
@@ -161,13 +163,16 @@
     \path [line] (bit.south)   |- ($(fpga)-(0,3.5)$) -- ($(fpga)-(0,1.6)$);
 
     \path [line] (dlcli)   |- ($(dlcli)-(0,0.7)$) -- ($(fpga)+(0.2,1.6)$);
-    \path [line] (dlgui)   |- ($(dlgui)-(0,0.7)$) -- ($(fpga)+(-0.2,1.6)$);
-    \path [line] ($(dlgui.south)-(0.5,0)$)   |- ($(dlgui)-(0.5,1)$) -| (tstconf.south);
+    \path [line] ($(dlgui.south)+(0,0)$)   |- ($(dlgui)-(0,0.7)$) -- ($(fpga)+(-0.2,1.6)$);
+    \path [line] ($(dlgui.south)-(1.0,0)$)   |- ($(dlgui)-(1,1)$) -| (tstconf.south);
     \path [line] (tstconf) -| ($(dlcli.north)-(0.25,0)$);
     \path [line] (tstconf) -| ($(dlgui.north)-(0.25,0)$);
 
+    \path [line] ($(dlgui.south)-(0.5,0)$) |- (inv3.center) -- (templ);
+
+
 
 
 \end{tikzpicture}
 
-%\end{document}
\ No newline at end of file
+%\end{document}