Commit 7c041c64 authored by Christian Fibich's avatar Christian Fibich Committed by Stefan Tauner
Browse files

Constraings for Zybo VGA Demo

parent d2d4c38f
###==== BEGIN Header
# Synopsys, Inc. constraint file
# /home/fibich/git/vecs/fiji/fiji_public/docs/demos/tmr_vga/fiji/zybo_test_1/synp/spriteflyer_top.fdc
# Written on Thu Apr 13 16:44:56 2017
# by Synplify Pro, J-2014.09-SP2 FDC Constraint Editor
# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
# These sections are generated from SCOPE spreadsheet tabs.
###==== END Header
###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
###==== END Collections
###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
create_clock {p:s_clk_i} -period {8}
###==== END Clocks
###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
###==== END "Generated Clocks"
###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
###==== END Inputs/Outputs
###==== BEGIN Registers - (Populated from tab in SCOPE, do not edit)
###==== END Registers
###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
###==== END "Delay Paths"
###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
###==== END Attributes
###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
###==== END "I/O Standards"
###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
###==== END "Compile Points"
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