Commit 7a461a4d authored by Stefan Tauner's avatar Stefan Tauner
Browse files

instrument: fix support of ports in submodules

parent 6a0fc692
......@@ -566,21 +566,18 @@ sub instrument_net {
# If instrumented net is a vector we will need an intermediate bus
if (defined($net->msb)) {
$driver_is_vector = 1;
# If port is vector change type of existing non-instrumented input to wire -
# practically transforming it to an ordinary wire that can easily be intrumented
}
# Change type of existing non-instrumented input to wire -
# practically transforming it to an ordinary wire that can easily be intrumented.
$logger->debug("Transforming previous port named \"". $connection->name . "\" into an ordinary wire");
$connection->net->decl_type(undef);
$connection->net->net_type("wire");
# Unsetting the port<->net inter-references forces their automatic re-setting at link time
$connection->net->port(undef);
$logger->debug("Transforming previous port named \"". $connection->name . "\" into an ordinary wire");
}
# FIXME: rename port in instantiation of current module
$logger->warn("Instantiation of module \"" . $mod->name . "\" needs to change port \"" . $connection->name . "\" to \"$net_name_tmp\" - not supported yet...");
# if ($mod->is_top) {
# FIXME: add naming information for wrapper generator
# } else {
# }
$connection->net(undef);
# Eventually connect this port to the intermediate net by changing its name
$logger->debug("Connecting (input) port \"" . $connection->name . "\" to intermediate net \"$net_name_tmp\"");
$connection->name($net_name_tmp);
$connection->name($net_name_tmp); # NB: this will automatically change the cell's configuration on the next link() call.
} elsif (ref($connection) eq "Verilog::Netlist::ContAssign") {
# FIXME: concatenations
# If the driver is an assignment, replace the LHS with the intermediate net
......@@ -635,7 +632,6 @@ sub instrument_net {
# 3.) If original signal is a bus forward orignal data from tmp net to untouched bits of original signal
# 4.) Forward (injected bit of) intermediate net to FIC by assigning it to the output pin
#
my $net_tmp;
# If the name is already taken then assume we need to instrument another bit of a bus
# FIXME: maybe we should try harder to find out the reason why _check_name_in_hierarchy failed
if (defined($name_check)) {
......@@ -644,7 +640,6 @@ sub instrument_net {
$logger->error($err);
return $err;
}
$net_tmp = $mod->find_net($net_name_tmp);
# We need to undo the previous assignment of the respective bit
foreach my $statement ($mod->statements) {
if ($statement->rhs =~ /^[ \t]*~?[ \t]*\Q$net_name_tmp\E(\[(\Q$msb\E)\])?$/) {
......@@ -657,22 +652,26 @@ sub instrument_net {
generate_contassign($mod, $net_name."[".$msb."]", $ip->net->name);
} else {
# 2.) Generate intermediate (tmp) net for easier input and output routing
# For ports we don't need to do that ourselves because Verilog::Perl will
# generate a new apropriate net when linking the port.
if ($driver_is_port) {
$logger->debug("Intermediate " . ($driver_is_port ? 'port' : 'wire') . " named \"" . $net_name_tmp . (defined($net->msb) ? "[" . $net->msb .":". $net->lsb . "]" : "") . "\" to patch \"$net_name\" will be generated automatically later");
} else {
# If the driver is a vector then we will generate a vectored intermediate net as well.
# However, if the driver is a single-bit net or a single bit of a vector we get away
# without an intermediate net.
# However, if the driver is a single-bit net or a single bit of a vector we generate
# a simple intermediate net (and could get away with none at all actually).
my @net_cfg = (name => $net_name_tmp);
push(@net_cfg, net_type => 'input') if $driver_is_port;
if ($driver_is_vector) {
$logger->debug("Generating intermediate " . ($driver_is_port ? 'port' : 'wire') . " named \"" . $net_name_tmp . "[" . $net->msb .":". $net->lsb . "]\" to patch \"$net_name\"");
$logger->debug("Generating intermediate wire named \"" . $net_name_tmp . "[" . $net->msb .":". $net->lsb . "]\" to patch \"$net_name\"");
push(@net_cfg,
msb => $net->msb,
lsb => $net->lsb,
);
} else {
$logger->debug("Generating intermediate " . ($driver_is_port ? 'port' : 'wire') . " named \"" . $net_name_tmp . "\" to patch \"$net_name\"");
$logger->debug("Generating intermediate wire named \"" . $net_name_tmp . "\" to patch \"$net_name\"");
}
$mod->new_net(@net_cfg);
}
$net_tmp = $mod->new_net(@net_cfg,);
# 3+4.) Assign injected (and uninjected bits of vectors) to previous signal.
# Below we assign the altered signal from the FIC to the original signal.
......@@ -682,15 +681,14 @@ sub instrument_net {
if (!defined($net->msb)) {
# If the instrumented net is not a vector we simply assign the injected signal
generate_contassign($mod, $net_name, $ip->net->name);
} elsif (!defined($net_tmp->msb)) {
} elsif (!$driver_is_vector) {
# If the net is a vector but the driver was driving only one bit
# then we need to drive the originally driven bit only
generate_contassign($mod, $net_name."[".$msb."]", $ip->net->name);
} else {
# For drivers of complete busses we need to connect all non-instrumented bits of the tmp net
# additionally to preserve their unmodified values.
my ($low, $high) = _extract_low_high($net_tmp->lsb, $net_tmp->msb);
my ($low, $high) = _extract_low_high($net->lsb, $net->msb);
for (my $i = $low ; $i <= $high ; $i++) {
if ($i == $msb) {
generate_contassign($mod, $net_name."[".$i."]", $ip->net->name);
......@@ -702,7 +700,8 @@ sub instrument_net {
}
# 5.) Connect the tmp net to the output pin that forwards the signal to the FIC
if (!defined($net_tmp->msb)) {
# If the driver is not a vector a simple assignment is fine, else
if (!$driver_is_vector) {
$logger->debug(" assigning \"" . $op->net->name . " = " . $net_name_tmp . "\"");
generate_contassign($mod, $op->net->name, $net_name_tmp);
} else {
......
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