Commit 6f7f3b10 authored by Stefan Tauner's avatar Stefan Tauner
Browse files

instrument: fix support of instrumenting a vector multiple times

parent bd474692
......@@ -654,6 +654,7 @@ sub instrument_net {
$logger->debug(" reassigning \"" . $net_name."[".$msb."] = " . $ip->net->name . "\"");
generate_contassign($mod, $net_name."[".$msb."]", $ip->net->name);
$driver_is_vector = 1;
} else {
# 2.) Generate intermediate (tmp) net for easier input and output routing
# For ports we don't need to do that ourselves because Verilog::Perl will
......
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