instrument: fix support of instrumenting a vector multiple times

bin/FIJI/Netlist.pm

@@ -654,6 +654,7 @@ sub instrument_net {
 
         $logger->debug("    reassigning \"" . $net_name."[".$msb."] = " . $ip->net->name . "\"");
         generate_contassign($mod, $net_name."[".$msb."]", $ip->net->name);
+        $driver_is_vector = 1;
     } else {
         # 2.) Generate intermediate (tmp) net for easier input and output routing
         # For ports we don't need to do that ourselves because Verilog::Perl will